公开(公告)号：US20170110536A1

公开(公告)日：2017-04-20

申请号：US14952877

申请日：2015-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/06 ,  G06F17/50 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

公开(公告)号：US20160358919A1

公开(公告)日：2016-12-08

申请号：US14727875

申请日：2015-06-02

Applicant: United Microelectronics Corp.

Inventor： Kuan-Chuan Chen ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shih-Yin Hsiao

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/0653 ,  H01L21/28238 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66613

Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.

Abstract translation: 提供一种用于形成高压晶体管的方法。 首先，提供具有顶面的基板，接着在基板上形成热氧化层。 去除热氧化层的至少一部分以在衬底中形成凹部，其中凹部的底表面低于衬底的顶表面。 在凹部中形成栅极氧化层，然后在栅极氧化物层上形成栅极结构。 该方法还包括在衬底中形成源极/漏极区域。

公开(公告)号：US08937352B2

公开(公告)日：2015-01-20

申请号：US14181733

申请日：2014-02-17

Applicant: United Microelectronics Corp.

Inventor： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Chih-Wei Hsu ,  Po-Ching Chuang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract translation: 植入层的布局图案至少包括线性区域和至少非线性区域。 线性区域包括容纳第一掺杂剂的多个第一图案，并且非线性区域包括多个第二图案以容纳第一掺杂剂。 线性区域邻接非线性区域。 此外，线性区域中的第一图案的图案密度小于非线性区域中的第二图案的图案密度。