公开(公告)号：US20140159155A1

公开(公告)日：2014-06-12

申请号：US14181733

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Chih-Wei Hsu ,  Po-Ching Chuang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract translation: 植入层的布局图案至少包括线性区域和至少非线性区域。 线性区域包括容纳第一掺杂剂的多个第一图案，并且非线性区域包括多个第二图案以容纳第一掺杂剂。 线性区域邻接非线性区域。 此外，线性区域中的第一图案的图案密度小于非线性区域中的第二图案的图案密度。

公开(公告)号：US12055849B2

公开(公告)日：2024-08-06

申请号：US17363380

申请日：2021-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Lun Tseng ,  Yen-Ting Pan ,  Chih-Wei Hsu

IPC: G03F1/36 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F1/36 ,  G03F7/70441 ,  H01L21/0274

Abstract: A method for correcting a semiconductor mask pattern includes steps as follows: A pattern to be corrected in the semiconductor mask pattern is divided into a plurality of sub-blocks that are symmetrical to and coincide with each other. Then, an optical proximity correction (OPC) step is performed on one of the plurality of sub-blocks to obtain a modified template. At least one copy template is generated according to the modified template corresponding to the other ones of the plurality of sub-blocks. The modified template and the at least one copy template are spliced to form a correcting pattern to replace the original pattern to be corrected.

公开(公告)号：US20130326436A1

公开(公告)日：2013-12-05

申请号：US13951095

申请日：2013-07-25

Applicant: United Microelectronics Corp.

Inventor： Jui-Yun Chang ,  Jian-Cheng Chen ,  I-Jen Kao ,  Chih-Wei Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

Abstract translation: 本发明涉及一种用于在布局上检查模具密封环的方法。 该方法包括以下步骤：接收与至少具有对应于布局的文本信息的设备对应的布局的数字数据库。 接收与布局相对应的磁带输出信息。 根据布局的数字数据库和输出信息进行检查处理，同时，通过使用布局的数字数据库，文本信息来执行用于设计与布局相对应的掩模图案的掩模设计过程 和输出信息。 检查处理的结果记录在与布局对应的检查表中。

公开(公告)号：US11475202B1

公开(公告)日：2022-10-18

申请号：US17323893

申请日：2021-05-18

Applicant: United Microelectronics Corp.

Inventor： Ming-Hsien Kuo ,  Chih-Wei Hsu ,  Song-Yi Lin

IPC: G06F30/30 ,  G03F1/36 ,  G03F7/20 ,  G06F30/398 ,  G06F30/392 ,  G06F119/18

Abstract: A method of designing a semiconductor device includes creating a library for test patterns on a frame and an on purpose violation layout on a main chip of a layout, and then creating filter marks according to the library. An OPC (optical proximity correction) is run using the layout, and an OPC verifying is performed for obtaining a pattern with hot spots to determine whether the hot spots are within the frame and the filter marks. When the hot spots are within the frame and the filter marks, a mask can be made. When the hot spots are outside the frame and the filter marks, it is necessary to check whether the hot spots need to be repaired. When the hot spots are within the frame and outside the filter marks, the hot spots are added into the library as data of the on purpose violation layout.

公开(公告)号：US08788980B2

公开(公告)日：2014-07-22

申请号：US13951095

申请日：2013-07-25

Applicant: United Microelectronics Corp.

Inventor： Jui-Yun Chang ,  Jian-Cheng Chen ,  I-Jen Kao ,  Chih-Wei Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

Abstract translation: 本发明涉及一种用于在布局上检查模具密封环的方法。 该方法包括以下步骤：接收与至少具有对应于布局的文本信息的设备对应的布局的数字数据库。 接收与布局相对应的磁带输出信息。 根据布局的数字数据库和输出信息进行检查处理，同时，通过使用布局的数字数据库，文本信息来执行用于设计与布局相对应的掩模图案的掩模设计过程 和输出信息。 检查处理的结果记录在与布局对应的检查表中。

公开(公告)号：US08937352B2

公开(公告)日：2015-01-20

申请号：US14181733

申请日：2014-02-17

Applicant: United Microelectronics Corp.

Inventor： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Chih-Wei Hsu ,  Po-Ching Chuang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract translation: 植入层的布局图案至少包括线性区域和至少非线性区域。 线性区域包括容纳第一掺杂剂的多个第一图案，并且非线性区域包括多个第二图案以容纳第一掺杂剂。 线性区域邻接非线性区域。 此外，线性区域中的第一图案的图案密度小于非线性区域中的第二图案的图案密度。

公开(公告)号：US20220390828A1

公开(公告)日：2022-12-08

申请号：US17341342

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Han Huang ,  Chih-Wei Hsu

IPC: G03F1/36

Abstract: A method of making mask patterns includes the following steps. A first octagon feature is created, wherein the first octagon feature includes first sides, second sides orthogonal to the first sides, and third sides, wherein each of the third sides connects the corresponding first side to the corresponding second side. An optical proximity correction (OPC) process is applied by using a computer to parallel shift the first sides, the second sides and the third sides of the first octagon feature respectively, and thus to create a second octagon feature. The second octagon feature is applied to make a pattern of a photomask. A method of forming a pattern in a layer is also provided, which includes printing a circular pattern on a surface of a layer by using an octagon pattern of a photomask.