公开(公告)号：US20130100436A1

公开(公告)日：2013-04-25

申请号：US13281232

申请日：2011-10-25

Applicant: Warren Jackson ,  Zhiyong Li

Inventor： Warren Jackson ,  Zhiyong Li

IPC: G01N21/01 ,  B29D11/00 ,  B01D35/00 ,  B29C53/04 ,  B01D29/07 ,  C25B7/00

CPC classification number: G01N21/658 ,  B29D11/0074

Abstract: Molecular filters are disclosed herein. An example of the molecular filter includes a rolled substrate having an interior surface and opposed ends that are substantially orthogonal to the interior surface. The rolled substrate defines a layer and a fluid flow path extending from one of the opposed ends to another of the opposed ends. A template is positioned on the interior surface of the rolled substrate. The template includes a matrix, and molecule template locations formed in the matrix.

Abstract translation: 本文公开了分子过滤器。 分子过滤器的一个实例包括具有内表面和基本上正交于内表面的相对端的轧制衬底。 卷绕的基板限定了从相对端中的一个延伸到相对端中的另一个的层和流体流动路径。 模板位于轧制衬底的内表面上。 模板包括在矩阵中形成的矩阵和分子模板位置。

公开(公告)号：US20120113087A1

公开(公告)日：2012-05-10

申请号：US13377804

申请日：2009-06-18

Applicant: Carl P. Taussig ,  Richard E. Elder ,  Warren Jackson ,  Hao Luo

Inventor： Carl P. Taussig ,  Richard E. Elder ,  Warren Jackson ,  Hao Luo

IPC: G09G3/32 ,  G09G5/00 ,  H01L21/02

CPC classification number: G09G3/3233 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2310/0254 ,  G09G2320/043 ,  H01L27/1255

Abstract: Pixel circuits (100, 300) and related methods are provided. In this regard, a representative pixel circuit includes: a data line (104, 304) operative to carry a data signal; a select line (106, 306) operative to carry a select signal; a first thin film transistor (TFT) (T1, T1A) conductively coupled to the data line and to the select line; and a second TFT (T2, T2A) capacitively coupled to the first TFT, the second TFT being operative to drive an emissive load responsive to the data signal and the select signal; wherein the data signal is provided to the second TFT through capacitive coupling.

Abstract translation: 提供像素电路（100,300）和相关方法。 在这方面，代表像素电路包括：数据线（104,304），用于承载数据信号; 操作用于携带选择信号的选择线（106,306）; 与数据线和选择线导电耦合的第一薄膜晶体管（TFT）（T1，T1A）; 以及电容耦合到所述第一TFT的第二TFT（T2，T2A），所述第二TFT可操作以响应于所述数据信号和所述选择信号来驱动发射负载; 其中通过电容耦合将数据信号提供给第二TFT。

公开(公告)号：US08021935B2

公开(公告)日：2011-09-20

申请号：US12243073

申请日：2008-10-01

Applicant: Ping Mei ,  Hao Luo ,  Albert Hua Jeans ,  Angeles Marcia Almanza-Workman ,  Robert A. Garcia ,  Warren Jackson ,  Carl P. Taussig ,  Craig M. Perlov

Inventor： Ping Mei ,  Hao Luo ,  Albert Hua Jeans ,  Angeles Marcia Almanza-Workman ,  Robert A. Garcia ,  Warren Jackson ,  Carl P. Taussig ,  Craig M. Perlov

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  Y10S438/942

Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.

Abstract translation: 用于平板显示器的背板的装置的制造方法包括在衬底上沉积薄膜层，形成覆盖薄膜层的3D模板，以及蚀刻3D模板和薄膜层以形成栅线和晶体管 从薄膜层。 然后可以在栅极线和晶体管上沉积绝缘或钝化层，使得可以在绝缘层上形成列或数据线。

公开(公告)号：US07817129B2

公开(公告)日：2010-10-19

申请号：US11590339

申请日：2006-10-30

Applicant: Warren Jackson ,  Carl Taussig ,  Hao Luo

Inventor： Warren Jackson ,  Carl Taussig ,  Hao Luo

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0254 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2320/043 ,  G09G2330/08

Abstract: An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

Abstract translation: 描述了有源矩阵阵列内的集成线选择装置。 该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。 该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极， 通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

公开(公告)号：US07795062B2

公开(公告)日：2010-09-14

申请号：US11696079

申请日：2007-04-03

Applicant: Carl P. Taussig ,  Ping Mei ,  Hao Luo ,  Warren Jackson

Inventor： Carl P. Taussig ,  Ping Mei ,  Hao Luo ,  Warren Jackson

IPC: H01L21/00

CPC classification number: H01L27/14683 ,  G06K9/0002 ,  H01L27/14678 ,  H01L29/84

Abstract: This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs.

Abstract translation: 本发明提供一种形成至少一个压力开关薄膜器件的方法。 该方法包括提供衬底并将多个薄膜器件层作为堆叠沉积在衬底上。 在多个薄膜器件层上提供印模的3D模板结构。 然后蚀刻多个薄膜器件层和3D模板结构，并且至少一个薄膜器件层被切削以提供多个对准的电接触对和相邻的间隔柱。 提供多个单独的电触点的柔性膜沉积在间隔柱上，分开的电触点与触点对重叠。 间隔柱在电触点和触点对之间提供间隙。

公开(公告)号：US20080100302A1

公开(公告)日：2008-05-01

申请号：US11590349

申请日：2006-10-30

Applicant: Warren Jackson ,  Carl Taussig

Inventor： Warren Jackson ,  Carl Taussig

IPC: G01R31/08

CPC classification number: G01N27/221 ,  G01R31/2806

Abstract: An apparatus and method for measuring and monitoring layer properties in web-based processes are described. The apparatus includes multiple electrode devices adjacently positioned on a surface of a web material, which advances with a predetermined speed. The electrode devices perform measurements of electrical parameters of a layer of the web material and provide an electrical signal to a layer deposition system for further adjustment of layer properties of the layer.

Abstract translation: 描述了一种用于在基于web的过程中测量和监测层属性的装置和方法。 该装置包括相邻地定位在幅材材料的表面上的多个电极装置，其以预定速度前进。 电极装置执行网状材料层的电参数的测量，并向层沉积系统提供电信号，以进一步调整层的层性质。

公开(公告)号：US07291564B1

公开(公告)日：2007-11-06

申请号：US11414411

申请日：2006-04-28

Applicant: Warren Jackson

Inventor： Warren Jackson

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L22/26

Abstract: A method and system for facilitating etching. Specifically, the method includes incorporating a fluorescent marker in a layer of a grouping of patterned layers. Etching of the group of patterned layers is controlled based upon the fluorescent marker.

Abstract translation: 一种便于蚀刻的方法和系统。 具体地，该方法包括在图案化层组的层中并入荧光标记物。 基于荧光标记物控制图案层组的蚀刻。

公开(公告)号：US20060291872A1

公开(公告)日：2006-12-28

申请号：US11169083

申请日：2005-06-28

Applicant: Ping Mei ,  Warren Jackson

Inventor： Ping Mei ,  Warren Jackson

IPC: G03G15/00

CPC classification number: B41J29/393 ,  B41J2/17546 ,  G03G15/0848 ,  G03G2215/0695

Abstract: Provided is an article of manufacturer with anti-counterfeit properties a consumable, having taggant nanoparticles dispersed within it. Each taggant nanoparticle has at least one known physical characteristic such as, the taggant nanoparticles being a predetermined combination of nanoparticles providing at least two different taggant physical characteristics as a taggant code encoding product identification for the consumable so as to permit identification of the consumable. The physical characteristics in an embodiment include a combination of fluorescence, particle size, shape, and/or magnetic properties.

Abstract translation: 提供了一种具有防伪性能的制造商，其是消耗品，其中分散有标记剂纳米颗粒。 每个标记剂纳米颗粒具有至少一种已知的物理特性，例如，标记剂纳米颗粒是提供至少两种不同标签物理特征的预定组合的纳米颗粒，作为用于消耗品的标签牌编码产品标识，以便允许识别消耗品。 一个实施方案中的物理特性包括荧光，粒度，形状和/或磁性的组合。

公开(公告)号：US20060273147A1

公开(公告)日：2006-12-07

申请号：US11144203

申请日：2005-06-02

Applicant: Warren Jackson ,  Ping Mei

Inventor： Warren Jackson ,  Ping Mei

IPC: G06F17/00 ,  G06K5/00 ,  G06K19/00

CPC classification number: G07D7/02

Abstract: Disclosed is an anti-counterfeiting system. In a particular embodiment, the anti-counterfeiting system has a first structure having a plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. In addition, there is a second structure having a second plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. The first and second structures are configured to couple together. An alignment mechanism is operable to align the first structure to the second structure and establish proximate contact between the first and second pluralities of nanostructures. With respect to the first and second structures, each encodes part of an authentication key. The authentication key includes pre-determined elements and interaction modalities. The resolution of the structures makes them copy-resistant. An associated method of use is also provided.

公开(公告)号：US20060111881A1

公开(公告)日：2006-05-25

申请号：US10995665

申请日：2004-11-23

Applicant: Warren Jackson

Inventor： Warren Jackson

IPC: G06F17/10

CPC classification number: G06F17/11 ,  G06N5/003

Abstract: A specialized processor includes an objective function evaluator responsive to a state vector; and a solver, responsive to an output of the evaluator, for finding an optimal solution to the state vector. The processor can form a building block of a larger system.

Abstract translation: 专用处理器包括响应于状态向量的目标函数评估器; 以及响应于评估器的输出的求解器，以找到状态向量的最优解。 处理器可以形成更大系统的构建块。