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公开(公告)号：US08808645B2
公开(公告)日：2014-08-19
申请号：US13281232
申请日：2011-10-25
Applicant: Warren Jackson , Zhiyong Li
Inventor： Warren Jackson , Zhiyong Li
CPC classification number: G01N21/658 , B29D11/0074
Abstract: Molecular filters are disclosed herein. An example of the molecular filter includes a rolled substrate having an interior surface and opposed ends that are substantially orthogonal to the interior surface. The rolled substrate defines a layer and a fluid flow path extending from one of the opposed ends to another of the opposed ends. A template is positioned on the interior surface of the rolled substrate. The template includes a matrix, and molecule template locations formed in the matrix.
Abstract translation: 本文公开了分子过滤器。 分子过滤器的一个实例包括具有内表面和基本上正交于内表面的相对端的轧制衬底。 卷绕的基板限定了从相对端中的一个延伸到相对端中的另一个的层和流体流动路径。 模板位于轧制衬底的内表面上。 模板包括在矩阵中形成的矩阵和分子模板位置。
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公开(公告)号：US20130100436A1
公开(公告)日：2013-04-25
申请号：US13281232
申请日：2011-10-25
Applicant: Warren Jackson , Zhiyong Li
Inventor： Warren Jackson , Zhiyong Li
CPC classification number: G01N21/658 , B29D11/0074
Abstract: Molecular filters are disclosed herein. An example of the molecular filter includes a rolled substrate having an interior surface and opposed ends that are substantially orthogonal to the interior surface. The rolled substrate defines a layer and a fluid flow path extending from one of the opposed ends to another of the opposed ends. A template is positioned on the interior surface of the rolled substrate. The template includes a matrix, and molecule template locations formed in the matrix.
Abstract translation: 本文公开了分子过滤器。 分子过滤器的一个实例包括具有内表面和基本上正交于内表面的相对端的轧制衬底。 卷绕的基板限定了从相对端中的一个延伸到相对端中的另一个的层和流体流动路径。 模板位于轧制衬底的内表面上。 模板包括在矩阵中形成的矩阵和分子模板位置。
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公开(公告)号：US20120043470A1
公开(公告)日：2012-02-23
申请号：US13264183
申请日：2009-04-15
Applicant: Hao Luo , Carl P. Taussig , Warren Jackson
Inventor： Hao Luo , Carl P. Taussig , Warren Jackson
IPC: G01T1/24
CPC classification number: H01J31/50 , G01T1/2018 , G01T1/2928
Abstract: An X-ray imaging apparatus includes a top transparent conductive layer and a bottom transparent conductive layer electrically connected to the top transparent conductive layer. The apparatus also includes an X-ray field modulator positioned adjacent to the bottom transparent conductive layer and an electro-optic layer positioned between the X-ray field modulator and the top transparent conductive layer. The X-ray field modulator is configured to modulate one of a resistance and a charge level therethrough when exposed to different X-ray levels to thereby create different levels of voltage drop across the electro-optic layer. In addition, the different levels of voltage drop causes varying optical properties to appear in the electro-optic layer.
Abstract translation: X射线成像装置包括顶部透明导电层和电连接到顶部透明导电层的底部透明导电层。 该装置还包括邻近底部透明导电层定位的X射线场调制器和位于X射线场调制器和顶部透明导电层之间的电光层。 X射线场调制器被配置为当暴露于不同的X射线水平时调制电阻和电荷水平中的一个，从而在电光层两端产生不同程度的电压降。 此外，电压降的不同水平导致在光电层中出现变化的光学性质。
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公开(公告)号：US08097400B2
公开(公告)日：2012-01-17
申请号：US11062384
申请日：2005-02-22
Applicant: Warren Jackson , Carl Taussig , Ping Mei
Inventor： Warren Jackson , Carl Taussig , Ping Mei
IPC: G03F7/20
CPC classification number: G03F7/0002 , B82Y10/00 , B82Y40/00
Abstract: Provided is a low cost system and method for forming electronic devices, especially large surface area devices. The process of imprint lithography is combined with alternate manufacturing techniques to fabricate the devices. Initially, a template imprints a three-dimensional pattern into a resist layer deposited on a flexible substrate. The resist layer is cured using ultraviolet light or other curing techniques. After curing, the 3-D pattern is modified using one of several techniques to include inkjetting, electrodeposition or laser patterning. In one embodiment, a semi-fluid material may be jetted into channels formed in the pattern, thereby forming conductive or insulating lead lines. Alternatively, a two-dimensional pattern may be jetted onto the resist layer. Final processing may include multiple etch-mask-etch steps. The integration of techniques into a single system provides a low cost, efficient method for manufacturing high quality, large surface area electronic devices.
Abstract translation: 提供一种用于形成电子装置，特别是大型表面积装置的低成本系统和方法。 压印光刻的过程与替代制造技术相结合以制造器件。 最初，模板将三维图案印刷到沉积在柔性基板上的抗蚀剂层中。 使用紫外线或其他固化技术固化抗蚀剂层。 固化后，使用几种技术之一来修改3-D图案，以包括喷墨，电沉积或激光图案化。 在一个实施例中，可以将半流体材料喷射到在图案中形成的通道中，从而形成导电或绝缘导线。 或者，可以将二维图案喷射到抗蚀剂层上。 最终处理可以包括多个蚀刻掩模蚀刻步骤。 将技术整合到单个系统中提供了用于制造高质量，大表面积电子器件的低成本，有效的方法。
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公开(公告)号：US07533905B2
公开(公告)日：2009-05-19
申请号：US11144203
申请日：2005-06-02
Applicant: Warren Jackson , Ping Mei
Inventor： Warren Jackson , Ping Mei
IPC: B42D15/00
CPC classification number: G07D7/02
Abstract: Disclosed is an anti-counterfeiting system. In a particular embodiment, the anti-counterfeiting system has a first structure having a plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. In addition, there is a second structure having a second plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. The first and second structures are configured to couple together. An alignment mechanism is operable to align the first structure to the second structure and establish proximate contact between the first and second pluralities of nanostructures. With respect to the first and second structures, each encodes part of an authentication key. The authentication key includes pre-determined elements and interaction modalities. The resolution of the structures makes them copy-resistant. An associated method of use is also provided.
Abstract translation: 披露了一种防伪系统。 在特定实施例中，防伪系统具有第一结构，其具有多个三维纳米结构，每个具有小于可见光波长的高度尺寸。 此外，存在具有第二多个三维纳米结构的第二结构，每个具有小于可见光波长的高度尺寸。 第一和第二结构被配置成耦合在一起。 对准机构可操作以将第一结构与第二结构对准并且在第一和第二多个纳米结构之间建立近似接触。 对于第一和第二结构，每个编码认证密钥的一部分。 验证密钥包括预定元素和交互模式。 结构的分辨率使其具有抗复制能力。 还提供了相关联的使用方法。
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Patent Agency Ranking
公开(公告)号：US20090108397A1
公开(公告)日：2009-04-30
申请号：US11932653
申请日：2007-10-31
Applicant: Warren Jackson , Carl P. Taussig , Ping Mei , Albert Jeans , Han-Jun Kim
Inventor： Warren Jackson , Carl P. Taussig , Ping Mei , Albert Jeans , Han-Jun Kim
IPC: H01L29/00
CPC classification number: H01L27/12 , H01L23/5221 , H01L2924/0002 , H01L2924/00
Abstract: This invention provides a thin film device with layer isolation structures. Specifically, a plurality of patterned thin film device layers provide a first rail and a second rail. There is at least one overpass between the first rail and the second rail. The overpass is defined by an array of spaced holes disposed transversely through the continuous material of the first rail on either side of the overpass. The holes are in communication with isolation voids adjacent to the second rail adjacent to the overpass.
Abstract translation: 本发明提供一种具有层隔离结构的薄膜器件。 具体地，多个图案化薄膜器件层提供第一轨道和第二轨道。 在第一轨道和第二轨道之间存在至少一个立交桥。 立交桥由立交桥两侧横向穿过第一轨道的连续材料的间隔开的孔组成。 这些孔与毗邻立交桥的第二轨道相邻的隔离空洞连通。
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公开(公告)号：US20080248605A1
公开(公告)日：2008-10-09
申请号：US11696079
申请日：2007-04-03
Applicant: Carl P. Taussig , Ping Mei , Hao Luo , Warren Jackson
Inventor： Carl P. Taussig , Ping Mei , Hao Luo , Warren Jackson
CPC classification number: H01L27/14683 , G06K9/0002 , H01L27/14678 , H01L29/84
Abstract: This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs.
Abstract translation: 本发明提供一种形成至少一个压力开关薄膜器件的方法。 该方法包括提供衬底并将多个薄膜器件层作为堆叠沉积在衬底上。 在多个薄膜器件层上提供印模的3D模板结构。 然后蚀刻多个薄膜器件层和3D模板结构，并且至少一个薄膜器件层被切削以提供多个对准的电接触对和相邻的间隔柱。 提供多个单独的电触点的柔性膜沉积在间隔柱上，分开的电触点与触点对重叠。 间隔柱在电触点和触点对之间提供间隙。
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公开(公告)号：US07394997B2
公开(公告)日：2008-07-01
申请号：US11169083
申请日：2005-06-28
Applicant: Ping Mei , Warren Jackson
Inventor： Ping Mei , Warren Jackson
IPC: G03G15/00
CPC classification number: B41J29/393 , B41J2/17546 , G03G15/0848 , G03G2215/0695
Abstract: Provided is an article of manufacturer with anti-counterfeit properties a consumable, having taggant nanoparticles dispersed within it. Each taggant nanoparticle has at least one known physical characteristic such as, the taggant nanoparticles being a predetermined combination of nanoparticles providing at least two different taggant physical characteristics as a taggant code encoding product identification for the consumable so as to permit identification of the consumable. The physical characteristics in an embodiment include a combination of fluorescence, particle size, shape, and/or magnetic properties.
Abstract translation: 提供了一种具有防伪性能的制造商，其是消耗品，其中分散有标记剂纳米颗粒。 每个标记剂纳米颗粒具有至少一种已知的物理特性，例如，标记剂纳米颗粒是提供至少两种不同标签物理特征的预定组合的纳米颗粒，作为用于消耗品的标签牌编码产品标识，以便允许识别消耗品。 一个实施方案中的物理特性包括荧光，粒度，形状和/或磁性的组合。
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9.发明授权Addressing circuit for a cross-point memory array including cross-point resistive elements 有权用于包括交叉点电阻元件的交叉点存储器阵列的寻址电路公开(公告)号：US06980465B2
公开(公告)日：2005-12-27
申请号：US10739350
申请日：2003-12-19
Applicant: Carl Taussig , Warren Jackson , Hao Luo
Inventor： Carl Taussig , Warren Jackson , Hao Luo
IPC: G11C17/14 , G11C5/02 , G11C7/00 , G11C8/00 , G11C8/10 , G11C11/00 , G11C16/02 , G11C17/16 , G11C17/18 , H01L27/10
CPC classification number: G11C17/16 , G11C5/025 , G11C8/10 , G11C13/0023 , G11C17/165 , G11C2213/71 , G11C2213/72 , G11C2213/77
Abstract: An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.
Abstract translation: 寻址电路可操作以寻址交叉点存储器阵列中的一个或多个存储器元件。 寻址电路包括用于寻址交叉点存储器阵列的第一组地址线和第二组地址线。 地址电路还包括上拉和下拉电路元件。 上拉和下拉电路元件和地址线都包括交叉点电阻元件。
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10.发明申请公开(公告)号：US20050162511A1
公开(公告)日：2005-07-28
申请号：US10767386
申请日：2004-01-28
Applicant: Warren Jackson
Inventor： Warren Jackson
Abstract: A method for displaying facial features includes generating an image with facial features on a nonplanar surface and positioning the image on the nonplanar surface to indicate a direction of gaze and enhance nonverbal communication associated with the facial features. The apparatus for displaying facial features includes a nonplanar surface, an image generation device that creates an image with facial features on the nonplanar surface and a positioning system that positions the image on the nonplanar surface to indicate a direction of gaze and enhance nonverbal communication associated with the facial features.
Abstract translation: 用于显示面部特征的方法包括在非平面表面上生成具有面部特征的图像，并将图像定位在非平面表面上以指示注视方向，并增强与面部特征相关联的非语言通信。 用于显示面部特征的装置包括非平面表面，在非平面上创建具有面部特征的图像的图像生成装置和将图像定位在非平面表面上以指示注视方向并增强与非平面表面相关联的非语言通信的定位系统 面部特征。
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