公开(公告)号：US08189728B1

公开(公告)日：2012-05-29

申请号：US13108151

申请日：2011-05-16

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G11B20/1816 ,  G11B20/10009 ,  G11B20/10444 ,  G11B2220/2541 ,  G11B2220/2562

摘要： A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after.

摘要翻译： 专门的结构通过使用过零点两侧的测量信号值平均二交叉零二值估计的结果来测量光存储器接口中的时钟到数据抖动。 在一个实施例中，第一估计在过零之前使用两个采样点和一个采样点之后，而第二估计在过零点之前使用一个采样点，并且采样两点之后。

公开(公告)号：US20120124454A1

公开(公告)日：2012-05-17

申请号：US12947962

申请日：2010-11-17

申请人： Jingfeng Liu ,  Hongwei Song ,  Haotian Zhang

发明人： Jingfeng Liu ,  Hongwei Song ,  Haotian Zhang

IPC分类号： G06F11/07

CPC分类号： H04L7/0334 ,  G11B20/10055 ,  G11B20/10231 ,  G11B20/10277 ,  G11B20/10296 ,  G11B2220/2516 ,  H04L7/0025

摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit operable to receive a data input and to provide corresponding digital samples, and a digital filter circuit operable to receive the digital samples and to provide a filtered output. A data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output, and a phase detector circuit operable to calculate an error feedback value based at least in part on the detected output and the digital samples.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了一种数据处理电路，其包括可操作以接收数据输入并提供对应的数字样本的模数转换器电路，以及可操作以接收数字样本并提供滤波输出的数字滤波器电路。 数据检测器电路可操作以对滤波的输出执行数据检测处理以产生检测的输出;以及相位检测器电路，可用于至少部分地基于检测的输出和数字样本来计算误差反馈值。

公开(公告)号：US20120069891A1

公开(公告)日：2012-03-22

申请号：US12887330

申请日：2010-09-21

申请人： Haotian Zhang ,  Hongwei Song ,  Jingfeng Liu ,  Yu Liao

发明人： Haotian Zhang ,  Hongwei Song ,  Jingfeng Liu ,  Yu Liao

IPC分类号： H03K5/159

CPC分类号： H03H17/0289 ,  H03H17/0294

摘要： Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

摘要翻译： 本发明的各种实施例提供了用于校准数据处理电路的系统和方法。 例如，讨论了一种用于校准数据处理电路的方法，其包括提供数字滤波器，提供检测器电路和提供模拟滤波器。 数字滤波器的操作至少部分地由对应于滤波器抽头约束值的滤波器抽头来控制。 检测器电路的操作至少部分地由目标参数控制。 模拟滤波器的操作至少部分地由作为多个模拟参数之一的模拟参数来控制。 所述方法还包括选择目标参数，以及基于所述目标参数来计算所述滤波器抽头约束值。 应用目标参数，计算滤波器抽头约束值和多个模拟参数中的每一个的组合以识别模拟参数。

公开(公告)号：US20120068870A1

公开(公告)日：2012-03-22

申请号：US12887327

申请日：2010-09-21

申请人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song

发明人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song

IPC分类号： H03M1/12

CPC分类号： H03M1/06 ,  H03M1/12

摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括模数转换器电路，数字滤波器电路，数据检测器电路，模拟滤波器电路和采样时钟产生电路的数据处理电路。 模数转换器电路可操作以接收数据输入并提供对应的数字采样。 数字滤波器电路可操作以接收数字样本并提供滤波输出。 数据检测器电路可操作以对滤波的输出执行数据检测处理，以产生检测的输出。 模拟滤波器电路可操作以接收数字样本并提供模拟输出。 采样时钟产生电路可操作以至少部分地基于所检测的输出和模拟输出来提供采样时钟。

公开(公告)号：US08054573B2

公开(公告)日：2011-11-08

申请号：US12663336

申请日：2008-10-27

申请人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song ,  Jeffrey P. Grundvig ,  Viswanath Annampedu

发明人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song ,  Jeffrey P. Grundvig ,  Viswanath Annampedu

IPC分类号： G11B5/60

CPC分类号： G11B5/59688 ,  G11B5/6029

摘要： Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium (278), and a SAM based fly-height adjustment circuit (214). The storage medium (278) includes a plurality of servo data regions (110) that each include a servo address mark (154). The SAM based fly-height adjustment circuit (214) receives the servo address mark (154) from the plurality of servo data regions (110) via the read/write head assembly (276), and calculates a first harmonics ratio (445) based on the received data. The first harmonics ratio (445) is compared with a second harmonics ratio (450) to determine an error (365) in the distance (295) between the read/write head assembly (276) and the storage medium (278).

摘要翻译： 本发明的各种实施例提供了用于确定飞行高度调节的系统和方法。 例如，本发明的各种实施例提供了包括存储介质，相对于存储介质（278）设置的读/写头组件和基于SAM的飞高调节电路（214））的存储设备。 存储介质（278）包括多个伺服数据区域（110），每个伺服数据区域包括伺服地址标记（154）。 基于SAM的飞高调整电路（214）经由读/写头组件（276）从多个伺服数据区（110）接收伺服地址标记（154），并且基于第一谐波比（445）计算 接收到的数据。 将第一谐波比（445）与第二谐波比（450）进行比较，以确定读/写头组件（276）和存储介质（278）之间的距离（295）中的误差（365）。

公开(公告)号：US07945009B1

公开(公告)日：2011-05-17

申请号：US11838617

申请日：2007-08-14

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： G11B20/1816 ,  G11B20/10009 ,  G11B20/10444 ,  G11B2220/2541 ,  G11B2220/2562

摘要： A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after. An existing clock associated with an internal analog-to-digital converter is used to evenly space the samples in time. To simplify the second-order estimate calculations, the three samples of the exemplary embodiment are give x values of −1, 0, and +1 respectively. Which of the two roots of the second-order estimates is used is based on the slope of the signal at the zero crossing.

摘要翻译： 专门的结构通过使用过零点两侧的测量信号值平均二交叉零二值估计的结果来测量光存储器接口中的时钟到数据抖动。 在一个实施例中，第一估计在过零之前使用两个采样点和一个采样点之后，而第二估计在过零点之前使用一个采样点，并且采样两点之后。 使用与内部模数转换器相关联的现有时钟来均匀地间隔样品。 为了简化二阶估计计算，示例性实施例的三个样本分别给出分别为-1,0和+1的x值。 使用二阶估计的两个根中的哪一个是基于过零点处的信号的斜率。

公开(公告)号：US20110075718A1

公开(公告)日：2011-03-31

申请号：US12570326

申请日：2009-09-30

申请人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song ,  Lingyan Sun

发明人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song ,  Lingyan Sun

IPC分类号： H04L27/01

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10481 ,  H03H17/0294

摘要： In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

摘要翻译： 在一个实施例中，（硬盘驱动器）读通道具有（DFIR均衡）滤波器，其抽头系数被自适应地更新。 复位控制器监视在滤波器下游产生的（LLR）信号，以自动确定何时复位滤波器，例如通过重新加载用户指定的抽头系数的初始集合。 对于LLR值，当复位控制器检测到过多的近期LLR值具有太低的置信度值时，复位控制器确定复位滤波器。 当在硬盘驱动器读取通道中实现时，复位控制器可以在硬盘驱动器的扇区内的读取操作期间复位一次或多次过滤器。

公开(公告)号：US20110072335A1

公开(公告)日：2011-03-24

申请号：US12562200

申请日：2009-09-18

申请人： Jingfeng Liu ,  Hongwei Song ,  Lingyan Sun

发明人： Jingfeng Liu ,  Hongwei Song ,  Lingyan Sun

IPC分类号： H03M13/03 ,  G06F11/00

CPC分类号： H03M13/1102 ,  H03M13/296 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343

摘要： In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

摘要翻译： 在一个实施例中，信号处理接收机具有分支量测校准（BMC）单元，其接收（i）来自信道检测器的四个硬判决位的集合，以及（ii）噪声估计。 BMC单元具有两个或多个更新块（例如抽头重量更新和/或偏置补偿块），其生成由信道检测器的分支度量单元使用的更新参数以改善信道检测。 两个或多个更新块基于（i）四个硬判决位的集合，（ii）噪声估计和（iii）带宽值）来生成更新的参数。 选择两个或多个更新块中的至少两个的带宽值使得它们彼此不同。 选择不同的带宽值可以通过选择彼此相同的带宽值来实现的比特错误率降低接收机的比特误码率。

公开(公告)号：US20110041028A1

公开(公告)日：2011-02-17

申请号：US12540283

申请日：2009-08-12

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： G06F1/04 ,  G06F12/06 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F3/05 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/27 ,  H03M13/3905 ,  H03M13/41 ,  H03M13/47 ,  H03M13/63 ,  H03M13/6331

摘要： Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples

摘要翻译： 本发明的各种实施例提供了用于数据处理系统的系统和方法。 作为一个示例，描述了包括模数转换器，在线定时循环和离线定时循环的数据处理电路。 模数转换器接收模拟输入并提供第一系列数据样本第一系列数据采样的每一位对应于在更新的采样时钟控制的时间的模拟输入。 在线定时循环至少部分地基于第一系列数据样本的处理版本来修改更新的采样时钟。 离线定时循环内插第一系列数据样本的导数，以产生模拟与使用自由运行时钟采样的模拟输入相对应的一系列数据样本的第二系列数据样本。 根据在第二系列数据样本中显示的平均频率偏移，内插第二系列数据样本以调整每个位

公开(公告)号：US07872823B2

公开(公告)日：2011-01-18

申请号：US12352540

申请日：2009-01-12

申请人： Jingfeng Liu ,  Hongwei Song ,  Jongseung Park ,  George Mathew ,  Yuan Xing Lee

发明人： Jingfeng Liu ,  Hongwei Song ,  Jongseung Park ,  George Mathew ,  Yuan Xing Lee

IPC分类号： G11B5/09

CPC分类号： G11B5/09 ,  G11B20/10009 ,  G11B20/10027 ,  G11B20/10046 ,  H03G3/30 ,  H03M1/185

摘要： Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.

摘要翻译： 本发明的各种实施例提供用于增益控制的系统和方法。 例如，本发明的一些实施例提供可变增益控制电路。 这种电路包括产生零强制反馈的零强制环路和产生最小均方反馈的最小均方环路。 误差量化电路使用零强制反馈和最小均方反馈基于阈值条件产生混合反馈。 可变增益放大器至少部分地由混合反馈的导数来控制。