公开(公告)号：US20120069891A1

公开(公告)日：2012-03-22

申请号：US12887330

申请日：2010-09-21

申请人： Haotian Zhang ,  Hongwei Song ,  Jingfeng Liu ,  Yu Liao

发明人： Haotian Zhang ,  Hongwei Song ,  Jingfeng Liu ,  Yu Liao

IPC分类号： H03K5/159

CPC分类号： H03H17/0289 ,  H03H17/0294

摘要： Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

摘要翻译： 本发明的各种实施例提供了用于校准数据处理电路的系统和方法。 例如，讨论了一种用于校准数据处理电路的方法，其包括提供数字滤波器，提供检测器电路和提供模拟滤波器。 数字滤波器的操作至少部分地由对应于滤波器抽头约束值的滤波器抽头来控制。 检测器电路的操作至少部分地由目标参数控制。 模拟滤波器的操作至少部分地由作为多个模拟参数之一的模拟参数来控制。 所述方法还包括选择目标参数，以及基于所述目标参数来计算所述滤波器抽头约束值。 应用目标参数，计算滤波器抽头约束值和多个模拟参数中的每一个的组合以识别模拟参数。

公开(公告)号：US20060028365A1

公开(公告)日：2006-02-09

申请号：US11244795

申请日：2005-10-06

申请人： Yannis Tsividis

发明人： Yannis Tsividis

IPC分类号： H03M3/00

CPC分类号： G06F7/5443 ,  H03H17/0289 ,  H03M1/125 ,  H03M1/36

摘要： A method of digitally processing an analog signal in continuous time includes producing a continuous-time digital signal from an analog signal via a technique that does not include periodic sampling, then producing one or more delayed versions of the continuous-time digital signal. Each delayed version is delayed by nT, where n is an integer greater than zero, and T is a delay interval. The method further includes multiplying the continuous-time digital signal and each of the delayed versions by one or more associated coefficients, so as to produce a set of products, then adding the set of products, so as to produce a sum value corresponding to the analog signal processed by a transfer function defined by the associated coefficients. The individual bit paths of the continuous-time digital signal are multiplied by the coefficients, and the resulting products are combined by a binary-weighted adder.

公开(公告)号：US20040233085A1

公开(公告)日：2004-11-25

申请号：US10730928

申请日：2003-12-10

申请人： ROHM CO., LTD.

发明人： Masakazu Fukuda

IPC分类号： H03M003/00 ,  H03D001/00

CPC分类号： H03H17/0289 ,  H03H15/00 ,  H03M3/504

摘要： The invention intends to reduce noises by resistors in an output filter for a delta sigma modulator. The output filter uses an FIR filter with constant current sources as the current source, extracts output data of the delta sigma modulator from each taps of a shift register, controls MOS transistors by the extracted delayed signals, attains currents weighted according to the FIR filter coefficients corresponding to the number of the taps from the constant current sources, adds the currents attained, and performs the current-to-voltage conversion of the currents thus attained by feedback resistors of a full differential operational amplifier.

摘要翻译： 本发明意图通过用于Δ-Σ调制器的输出滤波器中的电阻来减少噪声。 输出滤波器使用具有恒定电流源的FIR滤波器作为电流源，从移位寄存器的每个抽头提取Δ-Σ调制器的输出数据，通过提取的延迟信号控制MOS晶体管，获得根据FIR滤波器系数加权的电流 对应于来自恒定电流源的抽头数量，增加所获得的电流，并且对由全差分运算放大器的反馈电阻器获得的电流进行电流 - 电压转换。

公开(公告)号：US09219469B2

公开(公告)日：2015-12-22

申请号：US12887330

申请日：2010-09-21

申请人： Haotian Zhang ,  Hongwei Song ,  Jingfeng Liu ,  Yu Liao

发明人： Haotian Zhang ,  Hongwei Song ,  Jingfeng Liu ,  Yu Liao

IPC分类号： H03H7/30 ,  H04N11/02 ,  H03H17/02

CPC分类号： H03H17/0289 ,  H03H17/0294

摘要： Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

摘要翻译： 本发明的各种实施例提供了用于校准数据处理电路的系统和方法。 例如，讨论了一种用于校准数据处理电路的方法，其包括提供数字滤波器，提供检测器电路和提供模拟滤波器。 数字滤波器的操作至少部分地由对应于滤波器抽头约束值的滤波器抽头来控制。 检测器电路的操作至少部分地由目标参数控制。 模拟滤波器的操作至少部分地由作为多个模拟参数之一的模拟参数来控制。 所述方法还包括选择目标参数，以及基于所述目标参数来计算所述滤波器抽头约束值。 应用目标参数，计算滤波器抽头约束值和多个模拟参数中的每一个的组合以识别模拟参数。

公开(公告)号：US5724037A

公开(公告)日：1998-03-03

申请号：US447735

申请日：1995-05-23

申请人： Wai L. Lee

发明人： Wai L. Lee

IPC分类号： H03H17/02 ,  H03H17/06 ,  H03M3/02 ,  H03M3/00

CPC分类号： H03H17/0289 ,  H03H17/0628 ,  H03M3/462 ,  H03M3/364 ,  H03M3/43 ,  H03M3/452

摘要： A computed tomography imaging method includes receiving an analog beam intensity signal from a computed tomography scanner and converting the signal into a series of digital representations of the signal at successive points in time using a predetermined sample rate. Indications that a portion of the scanner has reached a certain position relative to the beam are received asynchronously with respect to the sample rate. The value of at least one of the digital representations is adjusted in response to the indications to obtain a corrected digital representation of the analog signal.

摘要翻译： 计算机断层摄影成像方法包括从计算机断层摄影扫描仪接收模拟光束强度信号，并使用预定采样率将信号在连续的时间点将信号转换为信号的一系列数字表示。 扫描仪的一部分相对于光束达到某一位置的指示相对于采样率异步地被接收。 响应于指示来调整数字表示中的至少一个的值以获得模拟信号的校正数字表示。

公开(公告)号：US3883727A

公开(公告)日：1975-05-13

申请号：US26904872

申请日：1972-07-05

申请人： STUART RICHARD L ,  BHOPALE ARVIND M

发明人： STUART RICHARD L ,  BHOPALE ARVIND M

IPC分类号： H03H17/02 ,  G06F1/02 ,  G06F15/34

CPC分类号： H03H17/0289 ,  H03H2218/12

摘要： A multi-level digital filter system applicable to modems is provided. The incoming data is read serially into M shift registers and read out in parallel by M further shift registers under the control of an M-bit clock, where M log2N and N is the number of levels. After appropriate conditioning by a logic control circuit, the parallel outputs are filtered separately by M digital shaping filters. The shaping filters each comprise a chain of shift registers the outputs of which are weighted by a resistor network and summed to produce a desired time response, which in an exemplary embodiment is the inverse Fourier transform of an ideal low-pass filter. Summing of the filter outputs produces an N-level signal.

摘要翻译： 提供了适用于调制解调器的多级数字滤波系统。 输入数据被串行读入M个移位寄存器，并在M位时钟控制下由M个另外的移位寄存器并行读出，其中M = log2N，N是电平数。 在通过逻辑控制电路适当调节之后，并行输出由M个数字整形滤波器分开滤波。 整形滤波器各自包括一组移位寄存器，其输出由电阻网络加权，并相加以产生期望的时间响应，其在示例性实施例中是理想低通滤波器的傅里叶逆变换。 滤波器输出的相加产生N电平信号。

公开(公告)号：US07663522B2

公开(公告)日：2010-02-16

申请号：US12073325

申请日：2008-03-04

申请人： Kimmo Koli

发明人： Kimmo Koli

IPC分类号： H03M3/00

CPC分类号： H03M3/344 ,  H03H17/0251 ,  H03H17/0289 ,  H03M3/358 ,  H03M3/402 ,  H03M3/424 ,  H03M3/43 ,  H03M3/454

摘要： A delta-sigma A/D converter includes a D/A converter realized with a mixed-mode comb filter connected in a feedback loop from the output of the A/D converter to the input of the A/D converter. The D/A converter is configured to predistort a feedback signal. The converter further includes an analogue filter at the input of the A/D converter. The analogue filter is configured to cancel the predistortion of the feedback signal.

摘要翻译： Δ-ΣA / D转换器包括用混合模式梳状滤波器实现的D / A转换器，其连接在从A / D转换器的输出到A / D转换器的输入端的反馈回路中。 D / A转换器被配置为预失真反馈信号。 转换器还包括在A / D转换器的输入处的模拟滤波器。 模拟滤波器被配置为消除反馈信号的预失真。

公开(公告)号：US07132972B2

公开(公告)日：2006-11-07

申请号：US10878155

申请日：2004-06-28

申请人： Yannis Tsividis

发明人： Yannis Tsividis

IPC分类号： H03M1/34

CPC分类号： G06F7/5443 ,  H03H17/0289 ,  H03M1/125 ,  H03M1/36

摘要： A method of digitally processing an analog signal in continuous time includes producing a continuous-time digital signal from an analog signal via a technique that does not include periodic sampling, then producing one or more delayed versions of the continuous-time digital signal. Each delayed version is delayed by nT, where n is an integer greater than zero, and T is a delay interval. The method further includes multiplying the continuous-time digital signal and each of the delayed versions by one or more associated coefficients, so as to produce a set of products, then adding the set of products, so as to produce a sum value corresponding to the analog signal processed by a transfer function defined by the associated coefficients. The individual bit paths of the continuous-time digital signal are multiplied by the coefficients, and the resulting products are combined by a binary-weighted adder.

摘要翻译： 在连续时间内数字处理模拟信号的方法包括通过不包括周期性采样的技术从模拟信号产生连续时间数字信号，然后产生连续时间数字信号的一个或多个延迟版本。 每个延迟版本被延迟nT，其中n是大于零的整数，T是延迟间隔。 该方法还包括将连续时间数字信号和每个延迟版本乘以一个或多个相关联的系数，以便产生一组产品，然后将产品集合相加，以产生对应于 由相关系数定义的传递函数处理的模拟信号。 将连续时间数字信号的各个位路径乘以系数，并将所得到的乘积由二进制加权加法器组合。

公开(公告)号：US20040263375A1

公开(公告)日：2004-12-30

申请号：US10878155

申请日：2004-06-28

申请人： Columbia University

发明人： Yannis Tsividis

IPC分类号： H03M001/34 ,  H03M001/62

CPC分类号： G06F7/5443 ,  H03H17/0289 ,  H03M1/125 ,  H03M1/36

摘要： A method of digitally processing an analog signal in continuous time includes producing a continuous-time digital signal from an analog signal via a technique that does not include periodic sampling, then producing one or more delayed versions of the continuous-time digital signal. Each delayed version is delayed by nT, where n is an integer greater than zero, and T is a delay interval. The method further includes multiplying the continuous-time digital signal and each of the delayed versions by one or more associated coefficients, so as to produce a set of products, then adding the set of products, so as to produce a sum value corresponding to the analog signal processed by a transfer function defined by the associated coefficients. The individual bit paths of the continuous-time digital signal are multiplied by the coefficients, and the resulting products are combined by a binary-weighted adder.

摘要翻译： 在连续时间内数字处理模拟信号的方法包括通过不包括周期性采样的技术从模拟信号产生连续时间数字信号，然后产生连续时间数字信号的一个或多个延迟版本。 每个延迟版本被延迟nT，其中n是大于零的整数，T是延迟间隔。 该方法还包括将连续时间数字信号和每个延迟版本乘以一个或多个相关联的系数，以便产生一组产品，然后将产品集合相加，以产生对应于 由相关系数定义的传递函数处理的模拟信号。 将连续时间数字信号的各个位路径乘以系数，并将所得到的乘积由二进制加权加法器组合。

公开(公告)号：US5995030A

公开(公告)日：1999-11-30

申请号：US526834

申请日：1995-09-12

申请人： Carlin Dru Cabler

发明人： Carlin Dru Cabler

IPC分类号： H03H17/02 ,  H03H17/06 ,  H03M1/74 ,  H03M3/02 ,  H03M1/66

CPC分类号： H03H17/0289 ,  H03M1/745 ,  H03M3/504

摘要： An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of current paths, where each path includes an active element, such as a transistor, having a relatively high output impedance, which is connected to a common current source, and to an op amp for current-to-voltage conversion. The relatively high output impedance of the active current steering element causes any error term resulting from offset at the op amp inputs to be minimized.

摘要翻译： 一种用于数模转换电路的有源电流转向半数字FIR滤波器，其包括具有1位数字输入流和多个输出抽头的移位寄存器，其中每个输出抽头提供1位信号， 具有逻辑1或逻辑0的值，以及多个电流路径，其中每个路径包括连接到公共电流源的具有相对较高输出阻抗的有源元件，例如晶体管，并且 用于电流至电压转换的运算放大器。 有源电流导向元件的相对高的输出阻抗导致由运算放大器输入端的偏移导致的任何误差项都被最小化。