公开(公告)号：USD622671S1

公开(公告)日：2010-08-31

申请号：US29358938

申请日：2010-04-01

Applicant: Yao-Ting Wang ,  Yu-Hung Su ,  Yeh-Ta Chien

Designer： Yao-Ting Wang ,  Yu-Hung Su ,  Yeh-Ta Chien

公开(公告)号：US07510444B2

公开(公告)日：2009-03-31

申请号：US11826545

申请日：2007-07-17

Applicant: Jui-Ming Chang ,  Yao-Ting Wang

Inventor： Jui-Ming Chang ,  Yao-Ting Wang

IPC: H01R24/00

CPC classification number: H01R13/2442 ,  H01R12/57 ,  H01R12/707 ,  H01R13/424

Abstract: A SIM card connector includes an insulating body and a plurality of electric terminals. The insulating body has accepting holes and accepting cavities. The electric terminal has a welded slice, a contact and a fixing portion. The welded slice and the contact are accepted in the accepting hole, the contact projects from the accepting hole. A lump is formed in one side of the fixing portion, the fixing portion accepted in the accepting cavities. While the SIM card connector passes through a SMT apparatus, the insulated body is soften and the lump is against the side wall of the accepting cavities for preventing the holding portion out of the insulated body. Therefore, the SIM card connector is welded firmly in the PCB of a mobile.

Abstract translation: SIM卡连接器包括绝缘体和多个电端子。 绝缘体具有接收孔和接收腔。 电气端子具有焊接片，触点和固定部。 焊接片和触点接受在接收孔中，触点从接收孔突出。 在固定部分的一侧形成有块状物，该接合腔体中的固定部分被接纳。 当SIM卡连接器通过SMT装置时，绝缘体软化，并且块体抵靠在容纳腔的侧壁上，以防止保持部分脱离绝缘体。 因此，SIM卡连接器牢固地焊接在移动电路的PCB上。

公开(公告)号：USD584232S1

公开(公告)日：2009-01-06

申请号：US29300079

申请日：2008-02-20

Applicant: Yu-Hung Su ,  Yao-Ting Wang ,  Ning-Lang Cheng

Designer： Yu-Hung Su ,  Yao-Ting Wang ,  Ning-Lang Cheng

公开(公告)号：US07360191B2

公开(公告)日：2008-04-15

申请号：US10984210

申请日：2004-11-08

Applicant: Li-Fu Chang ,  Yao-Ting Wang ,  Fang-Cheng Chang

Inventor： Li-Fu Chang ,  Yao-Ting Wang ,  Fang-Cheng Chang

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5036

Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract translation: 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。

公开(公告)号：US07356788B2

公开(公告)日：2008-04-08

申请号：US10173198

申请日：2002-06-18

Applicant: Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati

Inventor： Fang-Cheng Chang ,  Yao-Ting Wang ,  Yagyensh C. Pati

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.

Abstract translation: 一种用于对分级描述的集成电路布局执行操作的方法和装置，从而提供维护布局的原始层级。 该方法包括提供分层描述的布局作为第一输入，并提供与作为第二输入执行的操作相对应的特定操作标准集合。 然后可以根据特定的操作标准集在布局上执行掩模操作，其可以包括诸如OPC和诸如NOT和OR的逻辑操作的操作。 然后响应于布局操作​​产生包括对应于分层描述的布局的分层配置的校正数据的第一程序数据，使得如果第一程序数据被应用于平坦化布局，则输出包括表示执行操作的结果的数据 将生成布局。 由于第一程序数据以真正的分层格式维护，所以根据该方法操作的布局能够通过常规的设计规则检查器进行处理。 此外，该方法能够应用于所有类型的布局，包括浅色和暗场设计以及相移布局。

公开(公告)号：US07281226B2

公开(公告)日：2007-10-09

申请号：US10377341

申请日：2003-02-27

Applicant: Shao-Po Wu ,  Yao-Ting Wang

Inventor： Shao-Po Wu ,  Yao-Ting Wang

IPC: G06F17/50

CPC classification number: G03F1/30 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be placed to define critical features, wherein the pairs of shifters conform to predetermined design rules. After placement, phase information for the shifters associated with the set of critical features can be assigned. Complex designs can lead to phase-shift conflicts among shifters in the fabrication layout. An irresolvable conflict can be passed to the design process earlier than in a conventional processes, thereby saving valuable time in the fabrication process for printed circuits.

Abstract translation: 相移允许在打印的要素图层中生成非常窄的特征。 因此，形成具有关键特征的物理设计布局的制造布局通常包括为移位器提供布局。 具体地，可以放置移位器对以定义关键特征，其中移位器对符合预定的设计规则。 放置后，可以分配与该组关键特征相关联的移位器的相位信息。 复杂的设计可能导致制造布局中移位器之间的相移冲突。 可以比传统方法更早地将设计过程传递给设计过程，从而节省印刷电路制造过程中的宝贵时间。

公开(公告)号：US20050172251A1

公开(公告)日：2005-08-04

申请号：US10984443

申请日：2004-11-08

Applicant: Li-Fu Chang ,  Yao-Ting Wang ,  Fang-Cheng Chang

Inventor： Li-Fu Chang ,  Yao-Ting Wang ,  Fang-Cheng Chang

IPC: G06F17/50 ,  H01L20060101

CPC classification number: G06F17/5031 ,  G06F17/5036

Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract translation: 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。

公开(公告)号：US06904587B2

公开(公告)日：2005-06-07

申请号：US10327446

申请日：2002-12-20

Applicant: Chi-Ming Tsai ,  Chin-Hsen Lin ,  Yao-Ting Wang

Inventor： Chi-Ming Tsai ,  Chin-Hsen Lin ,  Yao-Ting Wang

IPC: G03F1/36 ,  G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Abstract translation: 光刻掩模布局被设计和逐步验证，以帮助减少产生掩模布局的时间量。 对于一个实施例，可以处理定义目标图案的布局以产生掩模布局，并且可以验证掩模布局以识别错误。 不是通过在一个或多个后续迭代处理和验证整个掩模布局进行纠错，而是可以从掩模布局去除或复制具有错误的子布局以进行单独的处理和验证。 由于定义子布局的数据量相对较小，所以减少了设计和验证掩码布局的时间。 然后，可以使用具有一个或多个经处理和验证的子布局的所得到的掩模布局来制造掩模组，以帮助例如在制造集成电路（IC）中打印目标图案。

公开(公告)号：US06622288B1

公开(公告)日：2003-09-16

申请号：US09823146

申请日：2001-03-29

Applicant: Yao-Ting Wang ,  Kent Richardson ,  Shao-Po Wu ,  Christophe Pierrat ,  Michael Sanie

Inventor： Yao-Ting Wang ,  Kent Richardson ,  Shao-Po Wu ,  Christophe Pierrat ,  Michael Sanie

IPC: G06F1750

CPC classification number: G03F1/30

Abstract: Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates one or more features logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. The adjustments rearrange features in a unit of the design layout to collect free space around a selected feature associated with the phase-shift conflict. With these techniques, a unit needing more space for additional shifters can obtain the needed space during the physical design process making the adjustment. The needed space so obtained allows the fabrication design process to avoid or resolve phase conflicts while forming a fabrication layout, such as a mask, for substantiating the design layout in a printed features layer, such as in an actual integrated circuit.

Abstract translation: 用于形成具有诸如集成电路布局的相移特征的设计布局的技术包括在第一物理设计布局中接收关于特定相移冲突的信息。 该信息指示与特定相移冲突逻辑关联的一个或多个特征。 然后根据该信息调整第一个物理设计布局以产生第二个设计布局。 调整重新排列设计布局中的功能，以收集与相移冲突相关的所选功能周围的可用空间。 利用这些技术，在进行调整的物理设计过程中，需要更多空间的单元可以获得额外的移位器的空间。 如此获得的所需空间允许制造设计过程避免或解决相位冲突，同时形成诸如掩模的制造布局，用于证实印刷特征层（例如在实际集成电路中）的设计布局。

公开(公告)号：US06584610B1

公开(公告)日：2003-06-24

申请号：US09823380

申请日：2001-03-29

Applicant: Shao-Po Wu ,  Yao-Ting Wang

Inventor： Shao-Po Wu ,  Yao-Ting Wang

IPC: G06F1750

CPC classification number: G03F1/30 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Phase shifting generates features in a printed features layer, such as a printed circuit, that are narrower than the features on a fabrication layout, such as a mask, projected onto the printed features layer using the same optical system without phase shifting. Techniques for forming a fabrication layout for a physical design layout having critical features employing phase shifting include techniques for providing a layout for shifters. The techniques include establishing placement of multiple pairs of shifters for a set of critical features. A critical feature employs phase shifting. The set of critical features constitutes a subset of all critical features in a layout. After establishing placement of the pairs of shifters, phase information for the shifters associated with the set of critical features is assigned. This and related techniques expedite resolving phase-shift conflicts in fabrication layouts for phase-shifted features. Complex designs can lead to phase-shift conflicts among shifters in the fabrication layout. According to these techniques, a conflict that cannot be resolved by a fabrication design process is passed to the design process earlier than in a conventional processes, saving valuable time in the fabrication process for printed circuits.

Abstract translation: 相移产生诸如印刷电路的印刷特征层中的特征，其比制造布局（例如掩模）上的特征窄，使用相同的没有相移的光学系统投影到印刷特征层上。 用于形成具有采用相移的关键特征的物理设计布局的制造布局的技术包括用于为移位器提供布局的技术。 这些技术包括为一组关键特征建立多对移位器的放置。 关键特征是采用相移。 一组关键特征构成布局中所有关键特征的一个子集。 在建立移位器对之后，分配与该组关键特征相关联的移位器的相位信息。该相关技术加速了相移特征制造布局中的相移冲突。 复杂的设计可能导致制造布局中移位器之间的相移冲突。 根据这些技术，制造设计过程无法解决的冲突比传统工艺更早地传递给设计过程，从而节省印刷电路制造过程中的宝贵时间。