公开(公告)号：US07131100B2

公开(公告)日：2006-10-31

申请号：US10316275

申请日：2002-12-10

Applicant: Chin-Hsen Lin ,  Chi-Ming Tsai

Inventor： Chin-Hsen Lin ,  Chi-Ming Tsai

IPC: G06F17/50 ,  G06F9/00

CPC classification number: G03F1/36 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Features of a mask, when close enough to one another, can cause unwanted phantom images to print on an integrated circuit. Advantageously, potential locations of phantom images can be automatically identified from a mask layout. This technique can include creating perimeters or rings around features in the mask layout (in one case, after proximity correction). An overlap of perimeters/rings can be assigned a particular weight such that areas of greater overlap have a higher weight and areas of less overlap have a lower weight. If the weight of an overlap area exceeds a trigger weight, then an evaluation point can be added to the mask layout, thereby identifying that layout location as a potential location of a phantom image. After simulation of the mask layout, that layout location can be analyzed to determine if a phantom image would print.

Abstract translation: 掩模的特征，当彼此足够接近时，可能会导致不想要的幻像图像在集成电路上打印。 有利地，可以从掩模布局自动识别幻影图像的潜在位置。 这种技术可以包括围绕掩模布局中的特征创建周长或环（在一种情况下，在邻近校正之后）。 周长/环的重叠可以被赋予特定的重量，使得更大重叠的区域具有较高的重量并且具有较小重叠的区域具有较低的重量。 如果重叠区域的重量超过触发权重，则可以将评估点添加到掩模布局，从而将该布局位置识别为幻影图像的潜在位置。 在模拟面具布局之后，可以分析该布局位置以确定幻影图像是否打印。

公开(公告)号：US06721928B2

公开(公告)日：2004-04-13

申请号：US10323565

申请日：2002-12-17

Applicant: Christophe Pierrat ,  Chin-Hsen Lin ,  Fang-Cheng Chang ,  Yao-Ting Wang

Inventor： Christophe Pierrat ,  Chin-Hsen Lin ,  Fang-Cheng Chang ,  Yao-Ting Wang

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract translation: 本发明使用基于实例的（IB）表示来减少验证从参考布局生成的经转换的布局所需的时间。 具体来说，从参考布局生成基于IB的表示。 基于IB的表示包括包括主实例单元和从实例单元的实例单元的集合。 需要模拟每组实例单元的一个子集，以验证转换后的布局。

公开(公告)号：US08312401B2

公开(公告)日：2012-11-13

申请号：US13005932

申请日：2011-01-13

Applicant: Iyun Leu ,  Chin Hsen Lin

Inventor： Iyun Leu ,  Chin Hsen Lin

IPC: G06F17/50

CPC classification number: G03F1/84 ,  G03F7/7065 ,  G06F17/5081

Abstract: A method for smart defect review is disclosed. The method includes pre-processing a design layout into a plurality of layout based pattern groups, dividing the design layout into a plurality of cells, overlapping the cells belong to the same layout based pattern groups, extracting a plurality of defect data of all defects on a wafer, constructing a plurality of layout based defect composite pattern groups, executing layout pattern match to obtain each individual layout based defect composite pattern group, performing some defect sample selection rules to each layout based defect composite pattern group, sorting the layout based defect composite pattern groups into different defect types, obtaining a defect image file by reviewing different sample number of defect image from each layout based defect composite pattern group, and generating a defect pattern library or a defect yield prediction by performing a defect yield diagnosis to the defect image file.

Abstract translation: 公开了一种智能缺陷评估方法。 该方法包括将设计布局预处理成多个基于布局的图案组，将设计布局划分成多个单元，将单元重叠为相同布局的图案组，提取多个缺陷数据， 构建多个基于布局的缺陷复合图案组，执行布局图匹配以获得基于每个单独布局的缺陷复合图案组，对每个基于布局的缺陷复合图案组执行一些缺陷样本选择规则，对基于布局的缺陷复合体进行排序 模式组成不同的缺陷类型，通过从每个基于布局的缺陷复合图案组中检查不同的缺陷图像样本数来获得缺陷图像文件，并且通过对缺陷图像执行缺陷产生诊断来生成缺陷图案库或缺陷产量预测 文件。

公开(公告)号：US20120185818A1

公开(公告)日：2012-07-19

申请号：US13005932

申请日：2011-01-13

Applicant: Iyun Leu ,  Chin Hsen Lin

Inventor： Iyun Leu ,  Chin Hsen Lin

IPC: G06F17/50

CPC classification number: G03F1/84 ,  G03F7/7065 ,  G06F17/5081

Abstract: A method for smart defect review is disclosed. The method includes pre-processing a design layout into a plurality of layout based pattern groups, dividing the design layout into a plurality of cells, overlapping the cells belong to the same layout based pattern groups, extracting a plurality of defect data of all defects on a wafer, constructing a plurality of layout based defect composite pattern groups, executing layout pattern match to obtain each individual layout based defect composite pattern group, performing some defect sample selection rules to each layout based defect composite pattern group, sorting the layout based defect composite pattern groups into different defect types, obtaining a defect image file by reviewing different sample number of defect image from each layout based defect composite pattern group, and generating a defect pattern library or a defect yield prediction by performing a defect yield diagnosis to the defect image file.

Abstract translation: 公开了一种智能缺陷评估方法。 该方法包括将设计布局预处理成多个基于布局的图案组，将设计布局划分成多个单元，将单元重叠为相同布局的图案组，提取多个缺陷数据， 构建多个基于布局的缺陷复合图案组，执行布局图匹配以获得基于每个单独布局的缺陷复合图案组，对每个基于布局的缺陷复合图案组执行一些缺陷样本选择规则，对基于布局的缺陷复合体进行排序 模式组成不同的缺陷类型，通过从每个基于布局的缺陷复合图案组中检查不同的缺陷图像样本数来获得缺陷图像文件，并且通过对缺陷图像执行缺陷产生诊断来生成缺陷图案库或缺陷产量预测 文件。

公开(公告)号：US06505327B2

公开(公告)日：2003-01-07

申请号：US09835313

申请日：2001-04-13

Applicant: Chin-hsen Lin

Inventor： Chin-hsen Lin

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell. If the changes result in a new node for which no instance has been created, the system creates a new instance for the node.

Abstract translation: 本发明的一个实施例提供了一种用于生成包括半导体芯片上的电路的布局的一组几何特征的基于实例的表示的系统。 该系统通过接收指定电路的布局的设计层级来操作，其中设计层级包括一组分层组织的节点。 在该设计层次结构中，给定节点指定几何特征，其可以由较低级几何特征组成。 这些较低级别的几何特征由出现在设计层次结构中给定节点下方的较低级节点表示。 此外，给定节点的布局由第一单元格指定，第一单元又指定设计层级中一个或多个节点的布局。 对于设计层次结构中的每个节点，系统确定与节点的兄弟和/或父节点以及可能的其他周围几何形状的交互如何改变由第一个单元格指定的节点的布局。 如果更改导致没有创建实例的新节点，系统将为该节点创建一个新实例。

公开(公告)号：US5841664A

公开(公告)日：1998-11-24

申请号：US614129

申请日：1996-03-12

Applicant: Yang Cai ,  Michael Chin-Hsen Lin

Inventor： Yang Cai ,  Michael Chin-Hsen Lin

IPC: G06F17/50 ,  G06F17/00 ,  G06F15/50

CPC classification number: G06F17/5077

Abstract: A method for optimal track assignment in a grid-based channel router. Initially, interconnection information is extracted from a global routing result. Multiple pin nets derived from the interconnection information are decomposed into simpler mapped segments. A channel grid map is then built and marked with existing objects. Next, a vertical constraint graph specifying the relative positions of the mapped segments is constructed. A first track is computed. A track assignment loop is repeated until all requisite connections are realized. The track assignment loop includes the steps of breaking cycles and long paths and collecting a set of feasible links. One or more weighting functions are assigned to each such feasible link. A dynamic programming approach is used to select an optimal set of feasible links according to the weighting functions. In addition, an optimal set of feasible links corresponding to unpreferred layers is collected by applying dynamic programming. Finally, the chosen feasible links are physically realized on the current track.

Abstract translation: 一种在网格通道路由器中实现最优轨道分配的方法。 最初，从全局路由结果中提取互连信息。 从互连信息导出的多个引脚网络被分解成更简单的映射段。 然后构建通道网格图并标记现有对象。 接下来，构造指定映射段的相对位置的垂直约束图。 计算第一个轨道。 重复轨道分配循环，直到实现所有必要的连接。 轨道分配循环包括断开循环和长路径并收集一组可行链接的步骤。 一个或多个加权函数被分配给每个这样的可行链路。 动态编程方法用于根据加权函数选择最佳可行链路集。 此外，通过应用动态规划来收集对与未优先层相对应的最佳可行链路集合。 最后，选择的可行链路在当前轨道上实际实现。

公开(公告)号：US5483461A

公开(公告)日：1996-01-09

申请号：US74961

申请日：1993-06-10

Applicant: Kaiwin Lee ,  Lu Chung ,  Chin-Hsen Lin ,  Yuh-Zen Liao ,  Stephen Wuu

Inventor： Kaiwin Lee ,  Lu Chung ,  Chin-Hsen Lin ,  Yuh-Zen Liao ,  Stephen Wuu

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.

Abstract translation: 本发明的电子设计自动化工具实施例包括五步骤处理。 在第一步中，对于单元格主机中任意形状的每个引脚主器件，识别引脚访问方向，其中放置通孔的区域将引脚连接到金属层，并且不会导致其他引脚的设计规则违反 - 主人，是物理界限在芯片的表面。 这样的区域被定义为针脚的“通孔区域”。 在第二步骤中，识别每个通孔区域内的至少一个“通孔”，如果将通孔放置在这些点上，则不会违反设计规则。 在第三步骤中，根据它们的通孔将通孔放置在每个单元实例上。 在第四步中，进行“迷宫路由”，以通过金属-1连接相邻的相同的网针。 在第五步中，通过迷宫路由器连接的引脚上的通孔被去除，如果当前网络的连接不完整，则在引脚上仅留下一个通孔。

公开(公告)号：US06904587B2

公开(公告)日：2005-06-07

申请号：US10327446

申请日：2002-12-20

Applicant: Chi-Ming Tsai ,  Chin-Hsen Lin ,  Yao-Ting Wang

Inventor： Chi-Ming Tsai ,  Chin-Hsen Lin ,  Yao-Ting Wang

IPC: G03F1/36 ,  G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Abstract translation: 光刻掩模布局被设计和逐步验证，以帮助减少产生掩模布局的时间量。 对于一个实施例，可以处理定义目标图案的布局以产生掩模布局，并且可以验证掩模布局以识别错误。 不是通过在一个或多个后续迭代处理和验证整个掩模布局进行纠错，而是可以从掩模布局去除或复制具有错误的子布局以进行单独的处理和验证。 由于定义子布局的数据量相对较小，所以减少了设计和验证掩码布局的时间。 然后，可以使用具有一个或多个经处理和验证的子布局的所得到的掩模布局来制造掩模组，以帮助例如在制造集成电路（IC）中打印目标图案。

公开(公告)号：US06560766B2

公开(公告)日：2003-05-06

申请号：US09917526

申请日：2001-07-26

Applicant: Christophe Pierrat ,  Chin-hsen Lin ,  Yao-Ting Wang ,  Fang-Cheng Chang

Inventor： Christophe Pierrat ,  Chin-hsen Lin ,  Yao-Ting Wang ,  Fang-Cheng Chang

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract translation: 本发明的一个实施例提供一种系统，其使用包括布局的一组几何特征的基于实例的表示来分析与半导体芯片上的电路相关的布局。 系统通过接收布局的表示来操作，其中所述表示定义包括一个或多个几何特征的多个节点。 接下来，系统通过识别布局中相同的节点实例的多次发生，将表示转换为基于实例的表示，其中可以进一步处理每个节点实例而不必考虑外部因素对节点实例的影响。 然后，系统通过仅处理每个节点实例一次对基于实例的表示进行进一步的处理，由此在布局中的多个节点实例的出现上不必重复该处理。