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    Semiconductor memory device
    51.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07467337B2

    公开(公告)日：2008-12-16

    申请号：US11102715

    申请日：2005-04-11

    Applicant: Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

    Inventor： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

    IPC: G06F11/00

    CPC classification number: G11C29/42 ,  G11C11/41

    Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

    Abstract translation: 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号以改变误差修正次数的上限时，寄存器改变上限值。 比较电路将误差校正次数与改变的上限进行比较。

    Semiconductor memory
    53.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US07373564B2

    公开(公告)日：2008-05-13

    申请号：US11092715

    申请日：2005-03-30

    Applicant: Akira Kikutake ,  Yasuhiro Onishi ,  Kuninori Kawabata

    Inventor： Akira Kikutake ,  Yasuhiro Onishi ,  Kuninori Kawabata

    IPC: G11C29/00

    CPC classification number: G11C29/42 ,  G11C11/401 ,  G11C29/10

    Abstract: A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

    Abstract translation: 普通写入数据选择电路在正常工作模式下工作，从而将通过外部数据终端接收的数据输出到根据地址选择的任何一个常规单元阵列。 测试写入控制电路在测试模式下操作，并且因此将测试数据写入与校验奇偶校验数据写入每个常规单元阵列中的奇偶校验存储单元的位置相对应的位置处的常规存储单元。 因此，由于可以使用公共测试模式来测试常规存储单元和奇偶校验存储单元，所以可以减少测试成本。

    Semiconductor memory device
    54.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20060156192A1

    公开(公告)日：2006-07-13

    申请号：US11102715

    申请日：2005-04-11

    Applicant: Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

    Inventor： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

    IPC: G11C29/00

    CPC classification number: G11C29/42 ,  G11C11/41

    Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

    Abstract translation: 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号（在图1 所示的情况下为外部上限提取信号）时，该寄存器改变数量的上限 错误更正，更改上限。 比较电路将误差校正次数与改变的上限进行比较。

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