公开(公告)号：US10649228B2

公开(公告)日：2020-05-12

申请号：US16694749

申请日：2019-11-25

Applicant: STMicroelectronics, Inc.

Inventor： Mark A. Lysinger ,  Pavan Nallamothu ,  Chih-Hung Tai ,  James L. Worley

IPC: G02B27/64 ,  H02K41/035 ,  H02P7/025

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

公开(公告)号：US10600786B2

公开(公告)日：2020-03-24

申请号：US15452049

申请日：2017-03-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Sylvain Maitrejean ,  Emmanuel Augendre ,  Pierre Morin ,  Shay Reboh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/266 ,  H01L21/268 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

公开(公告)号：US10573756B2

公开(公告)日：2020-02-25

申请号：US16228620

申请日：2018-12-20

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/165

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10560092B2

公开(公告)日：2020-02-11

申请号：US16274844

申请日：2019-02-13

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc. ,  STMicroelectronics (Alps) SAS

Inventor： Vanni Poletto ,  David F. Swanson ,  Giovanni Luca Torrisi ,  Laurent Chevalier

IPC: H03K17/687 ,  G01R19/165 ,  G05B11/42

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

公开(公告)号：US10541677B2

公开(公告)日：2020-01-21

申请号：US16156246

申请日：2018-10-10

Applicant: STMicroelectronics, Inc.

Inventor： Pavan Nallamothu

IPC: H03K3/00 ,  H03K3/012 ,  G05F1/575 ,  H03K17/687

Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.

公开(公告)号：US10531051B2

公开(公告)日：2020-01-07

申请号：US15978908

申请日：2018-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  James D. Allen

IPC: H04N7/18 ,  H04N5/232

Abstract: Embodiments of the present disclosure include a system and a method of accessing a system. An embodiment is a system including an imaging system including a controller and a first camera, the controller having a communication connection configured to transmit or receive content or control signals, and a mobile device including a second camera, the mobile device having a communication interface configured to transmit or receive content or control signals with the controller, the controller being configured to compare images from the first and second cameras to allow access to the controller from the mobile device.

公开(公告)号：US10459243B2

公开(公告)日：2019-10-29

申请号：US15927387

申请日：2018-03-21

Applicant: STMicroelectronics, Inc.

Inventor： Chih-Hung Tai ,  Felix Kim ,  Mark A. Lysinger

IPC: G02B27/64

Abstract: Various embodiments provide an optical image stabilization circuit that synchronizes its gyroscope and drive circuit using gyroscope data ready signals and gyroscope reset signals. In response to a gyroscope data ready signal, the optical image stabilization circuit synchronously obtains position measurements of a camera lens when power drive signals are not transitioning from one power level to another power level, and synchronously transitions the power drive signals simultaneously with gyroscope reset signals. By synchronizing the gyroscope and the drive circuit, the gyroscope and other onboard sensing circuits are isolated from noise generated by the drive circuit.

公开(公告)号：US10438856B2

公开(公告)日：2019-10-08

申请号：US13856325

申请日：2013-04-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L27/092

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

公开(公告)号：US10431682B2

公开(公告)日：2019-10-01

申请号：US15693952

申请日：2017-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/417

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

公开(公告)号：US10388659B2

公开(公告)日：2019-08-20

申请号：US15939108

申请日：2018-03-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/739 ,  H01L29/49

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.