公开(公告)号：US20160098506A1

公开(公告)日：2016-04-07

申请号：US14509037

申请日：2014-10-07

申请人： Amol Agarwal ,  Gaurav Goyal ,  Abhishek Mahajan ,  Sidharrtha Taneja

发明人： Amol Agarwal ,  Gaurav Goyal ,  Abhishek Mahajan ,  Sidharrtha Taneja

IPC分类号： G06F17/50 ,  H03K3/012 ,  H03K3/037

CPC分类号： G06F17/5031 ,  G06F2217/02 ,  G06F2217/84 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375

摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.

摘要翻译： 用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到 第一多路复用器和触发器模块的输出。 施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。 信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

公开(公告)号：US09306036B2

公开(公告)日：2016-04-05

申请号：US13953833

申请日：2013-07-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Michael Ganz

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02362 ,  G06F17/505 ,  G06F2217/02 ,  H01L21/0217 ,  H01L27/0207 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

摘要： Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.

摘要翻译： 提供了使用氮化物间隔物来保护半导体器件（例如，鳍式场效应晶体管器件（FinFET））的方法。 具体地说，在FinFET器件的一个氧化物和一组鳍片之上形成一个氮化物间隔物，以减轻随后的处理过程中的损坏。 在阻挡层之前沉积氮化物间隔物，以在未被光致抗蚀剂覆盖的FinFET器件的开放区域中的一组栅极的顶部上保护氧化物。 每个栅极顶部的氧化物将保留在所有块层中，以在随后的源/漏外延层分层期间提供硬掩模保护。 此外，由光致抗蚀剂或该组栅极打开和未覆盖的翅片仍然被氮化物间隔物保护。 因此，防止由于暴露于抗蚀剂剥离处理的翅片的非晶化而引起的翅片侵蚀，从而提高了器件的产率。

公开(公告)号：US20160070825A1

公开(公告)日：2016-03-10

申请号：US14662205

申请日：2015-03-18

申请人： Jin YAO ,  Rujia LIU ,  Decai HE ,  Kun BAI ,  Hao LI ,  Bo WANG ,  Xingnan ZHANG ,  Xin FANG

发明人： Jin YAO ,  Rujia LIU ,  Decai HE ,  Kun BAI ,  Hao LI ,  Bo WANG ,  Xingnan ZHANG ,  Xin FANG

IPC分类号： G06F17/50

CPC分类号： G06F17/5004 ,  G06F2217/02 ,  G06F2217/04 ,  G06T19/20 ,  G06T2210/04 ,  G06T2219/2021 ,  G06T2219/2024

摘要： The present invention discloses a method for automatically presenting a pavement scheme of decoration piles or marbles, including: step 1), recording tiles, pictures of marbles, mosaic modelings, patterns of cross banding line frames, patterns of modeling tiles of each brand into a database of the brand in a QEYJ software according to a QEYJ rule; step 2), transforming all kinds of designs of tiles or marbles and pavement manners into computer description language and formulas of functions; step 3), in a 3D stereo scene, by calling the computer description language and formulas of functions, re-transforming various tiles, pictures of marbles, mosaic modelings, patterns of cross banding line frames, patterns of modeling tiles by calculation, to present them in the 3D scene of a region to be paved; and step 4), by recording and transmitting, the pavement pattern produced in the 3D stereo scene may be calculated, transformed, and re-presented in other scenes. The present invention is particularly suitable for quickly presenting paving effects to consumers and owners in sales industry for tiles, marbles and the like, and has a significant promotion value.

摘要翻译： 本发明公开了一种自动呈现装饰桩或弹珠路面方案的方法，包括：步骤1）记录瓷砖，大理石图案，马赛克模拟，交叉条线框架图案，各品牌建模瓦片图案为 根据QEYJ规则，QEYJ软件中的品牌数据库; 步骤2），将各种瓷砖或大理石和路面设计的设计转化为计算机描述语言和功能公式; 步骤3），在3D立体场景中，通过调用计算机描述语言和功能公式，重新变换各种瓦片，大理石的图片，马赛克模拟，交叉条带线框架的图案，通过计算建模瓦片的图案，以呈现 他们在一个要铺成的地区的3D场景中; 和步骤4），通过记录和发送，可以在其他场景中计算，变换和重新呈现3D立体场景中产生的路面图案。 本发明特别适用于向瓷砖，大理石等销售行业的消费者和业主快速呈现铺路效果，并具有显着的促进价值。

公开(公告)号：US20160070824A1

公开(公告)日：2016-03-10

申请号：US14662178

申请日：2015-03-18

申请人： Jin YAO ,  Rujia LIU ,  Decai HE ,  Kun BAI ,  Hao LI ,  Bo WANG ,  Xingnan ZHANG ,  Xin FANG

发明人： Jin YAO ,  Rujia LIU ,  Decai HE ,  Kun BAI ,  Hao LI ,  Bo WANG ,  Xingnan ZHANG ,  Xin FANG

IPC分类号： G06F17/50 ,  G06T17/00

CPC分类号： G06F17/5004 ,  G06F2217/02 ,  G06F2217/04 ,  G06T17/00

摘要： The present invention discloses a method for generating a design scheme of a kitchen, characterized in that, the method includes: step 1) inputting combination data, 3D model data and the like of each series, type, size, material, modeling door and accessories and various cabinet body of each brand into a database of the brand in QEYJ software according to a QEYJ rule; step 2) transforming all kinds of cabinet designs and usage requirements of placement into computer description language and formulas of functions; step 3) determining s region to place cabinets, after a starting point, turning points, a finishing point and positions of a range hood and a sink are determined in a kitchen of a customer; for an island table and a bar table, determining a position by determining a starting point and a finishing point of placement; then, through the present invention, immediately calculating optimal design of placement for each series in a QEYJ system, and presenting it in a 2D interface. Since a data amount to be stored is relatively small in this method, the data may be easily transmitted to every computer mounted with QEYJ cabinet software over the world. Every upgraded cabinet series and every upgraded design fashion may be easily transmitted over the world.

摘要翻译： 本发明公开了一种生成厨房设计方案的方法，其特征在于，该方法包括：步骤1）输入每个系列的组合数据，3D模型数据等，类型，尺寸，材料，建模门和配件 各品牌的柜体根据QEYJ规则成为QEYJ软件中的品牌数据库; 步骤2）将各种柜体设计和使用要求转化为计算机描述语言和功能公式; 步骤3）在客户的厨房中确定起始点，转折点，终点和抽油烟机和水槽的位置之后确定区域放置橱柜; 通过确定放置的起点和终点来确定位置; 然后，通过本发明，立即计算QEYJ系统中每个系列的最佳布局设计，并将其呈现在2D界面中。 由于在该方法中要存储的数据量相对较小，因此数据可以容易地传输到世界上安装有QEYJ机柜软件的每台计算机。 每个升级柜系列和每一个升级的设计风格可能很容易传播到世界各地。

公开(公告)号：US20160048611A1

公开(公告)日：2016-02-18

申请号：US14460677

申请日：2014-08-15

申请人： VCE Company, LLC

发明人： Timothy Allen Cox ,  Jeffery Jon Hayward ,  Brian Keefe

IPC分类号： G06F17/50

CPC分类号： G06F17/5004 ,  G06F17/50 ,  G06F17/5086 ,  G06F2217/02 ,  G06F2217/06

摘要： A system, method, apparatus, and computer program product for generating an elevation plan for a computing system are disclosed. A method may include accessing a build specification identifying components to be included in the computing system. The method may also include accessing a set of component placement rules defining rules for placing components within a rack. The method may further include generating an elevation plan defining a respective mount position for each of a subset of the components within one or more racks based on the set of component placement rules.

摘要翻译： 公开了一种用于生成计算系统的升降计划的系统，方法，装置和计算机程序产品。 方法可以包括访问构建规范，以识别要包括在计算系统中的组件。 该方法还可以包括访问定义用于将组件放置在机架内的规则的组件放置规则集合。 该方法可以进一步包括基于组件放置规则的集合来生成为一个或多个机架中的部件的子集中的每一个定义相应安装位置的升高平面。

公开(公告)号：US09250649B2

公开(公告)日：2016-02-02

申请号：US14041152

申请日：2013-09-30

申请人： Dell Products L.P.

发明人： Hasnain Shabbir ,  Ramsundar Govindarajan ,  Dinesh Kunnathur Ragupathi

IPC分类号： G06F17/00 ,  G06F1/16 ,  G06Q10/00 ,  G06F17/50

CPC分类号： G06F1/16 ,  G06F1/206 ,  G06F17/5086 ,  G06F17/509 ,  G06F2217/02 ,  G06F2217/80 ,  G06Q10/00 ,  Y02D10/16

摘要： In accordance with embodiments of the present disclosure, a system may comprise a plurality of slots each configured to receive a modular information handling system, a plurality of air movers each configured to cool at least one modular information handling system disposed in at least one of the plurality slots, and a chassis management controller communicatively coupled to the plurality of slots and the plurality of air movers and configured to display a recommended placement of modular information handling systems in the plurality of slots based on at least one of: identities of slots populated with modular information handling systems, an airflow ranking of the plurality of slots, an impedance ranking of information handling systems disposed in the slots, and a workload of each of the information handling systems disposed in the slots.

摘要翻译： 根据本公开的实施例，系统可以包括多个槽，每个槽被配置为接收模块化信息处理系统，多个空气移动器，每个空气移动器被配置为冷却至少一个模块化信息处理系统，该至少一个模块化信息处理系统设置在至少一个 多个时隙，以及通信地耦合到所述多个时隙的所述机箱管理控制器，以及所述多个空气移动器，并且被配置为基于以下至少一个来显示所述多个时隙中的模块化信息处理系统的推荐布置：填充有 模块化信息处理系统，多个时隙中的气流分级，设置在时隙中的信息处理系统的阻抗等级以及设置在时隙中的每个信息处理系统的工作负载。

公开(公告)号：US20150379190A1

公开(公告)日：2015-12-31

申请号：US14841021

申请日：2015-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Tsun Chen ,  Jui-Cheng Huang ,  Yung-Chow Peng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5022 ,  G06F17/5068 ,  G06F2217/02 ,  G06F2217/06

摘要： A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices.

摘要翻译： 公开了一种用于对微机电装置进行建模的系统和方法。 一个实施例包括将微机电设计分离成单独的区域并分别对分开的区域进行建模。 参数化参数或参数方程可用于分开的模型。 单独的模型可以集成到MEMS器件模型中。 可以对MEMS器件模型进行测试和校准，然后可以用于为微机电器件的新设计建模。

公开(公告)号：US20150331974A1

公开(公告)日：2015-11-19

申请号：US14280494

申请日：2014-05-16

申请人： Configit A/S

发明人： Sathia Moorthy SUBBARAYAN ,  Henrik Reif ANDERSEN

IPC分类号： G06F17/50 ,  G06F7/02

CPC分类号： G06F17/50 ,  G06F7/02 ,  G06F17/5009 ,  G06F2217/02 ,  G06F2217/06

摘要： Methods, computer systems and computer readable storage mediums for configuring a product based on a product model are provided. The product model has variables and rules. Each variable is associated with a set of values. The rules represent inter-dependencies among the variables and values. The variables and rules define a product configuration problem to be solved. A Decomposable And Or Graph, DAOG, is generated. The DAOG represents the product model. Subsequently, values for the variables of the product model are iteratively set based on the DAOG.

摘要翻译： 提供了用于基于产品型号配置产品的方法，计算机系统和计算机可读存储介质。 产品型号有变量和规则。 每个变量都与一组值相关联。 规则表示变量和值之间的相互依赖关系。 变量和规则定义要解决的产品配置问题。 生成分解和图形，DAOG。 DAOG代表产品型号。 随后，基于DAOG迭代地设置产品模型的变量的值。

公开(公告)号：US20150302136A1

公开(公告)日：2015-10-22

申请号：US14733332

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US20150288371A1

公开(公告)日：2015-10-08

申请号：US14258571

申请日：2014-04-22

申请人： Dialog Semiconductor B.V.

发明人： Jan Prummel

IPC分类号： H03L7/107 ,  G06F17/50 ,  H03L7/093

CPC分类号： H03L7/1075 ,  G06F17/5045 ,  G06F2217/02 ,  G06F2217/08 ,  G06F2217/82 ,  G06F2217/84 ,  H03L7/093 ,  H03L7/10 ,  H03L7/1077

摘要： A method for constructing a phase locked loop begins with determining spurious frequency component criteria permitted within the PLL. A PLL filter prototype is selected with a desired settling time. A transfer function is generated based on the PLL transfer function that predicts the spurious components. A maximum level of the spurious components produced in the PLL is determined based on the maximum frequency step. If the maximum level of the spurious frequency components produced is too large, the order variable is incremented and the PLL transfer function is determined until the transfer function produces the spurious frequency components that meet the requirements. The components for a loop filter are selected based on the selected PLL transfer function. The adjustable frequency source tuning gain, the phase detector gain, the loop filter gain, and the divide factor are chosen to meet the requirements of the PLL transfer function.

摘要翻译： 用于构建锁相环的方法从确定PLL内允许的寄生频率分量标准开始。 选择具有所需建立时间的PLL滤波器原型。 基于预测杂散分量的PLL传递函数生成传递函数。 基于最大频率步长确定在PLL中产生的杂散分量的最大电平。 如果产生的杂散频率分量的最大电平太大，则顺序变量递增，并且确定PLL传递函数，直到传递函数产生满足要求的杂散频率分量。 基于选择的PLL传递函数选择环路滤波器的组件。 选择可调频率源调谐增益，相位检测器增益，环路滤波器增益和分频因子以满足PLL传递函数的要求。