公开(公告)号：US20180122095A1

公开(公告)日：2018-05-03

申请号：US15853046

申请日：2017-12-22

Applicant: Colamark (Guangzhou) Labeling Equipment Limited

Inventor： Kwok Ming Daniel Chan

IPC: G06T7/70 ,  B65G47/26 ,  H04N7/18 ,  B65G27/00 ,  B65G43/08

CPC classification number: G06T7/70 ,  B65G27/00 ,  B65G43/08 ,  B65G47/26 ,  B65G47/31 ,  B65G2811/0605 ,  G06K9/00 ,  G06T7/0004 ,  G06T7/20 ,  G06T2200/28 ,  G06T2207/10004 ,  G06T2207/30242 ,  H04N5/23229 ,  H04N7/183

Abstract: A method for counting and aggregating a pre-determined number of articles includes: driving, by a conveyor, an article stream to move to an end of the conveyor in a single layer state; conveying the article stream in a periodic motion; after the articles in the article stream leave the conveyor, accurately counting the number of the articles; and when a total number of articles in a combination of temporary storage bin is the same as a target number, transporting all articles in the combination of temporary storage bin to a storage device. Article batches are separately delivered to different temporary storage bins, and the total number of articles in temporary storage bins in different combinations is calculated, so as to obtain with a combination in which the number of articles is the same as the target number. The operation efficiency is improved and the manufacturing cost of device is reduced.

公开(公告)号：US09947114B2

公开(公告)日：2018-04-17

申请号：US14526220

申请日：2014-10-28

Applicant: ATI Technologies ULC

Inventor： Boris Ivanovic ,  Tiberiu Visan

IPC: G06T5/00 ,  G06T11/00

CPC classification number: G06T11/001 ,  G06T5/002 ,  G06T5/009 ,  G06T2200/28 ,  G06T2207/10016

Abstract: An apparatus and methods for modifying gradation in an image frame determine a blend factor indicating a first weighting associated with a previously processed portion of the image frame. The apparatus and methods generate a weighted value associated with a current region of the image frame based on the current region of the image frame and based on applying the first weighting to the previously processed portion of the image frame so as to modify the gradation in the image frame.

公开(公告)号：US09942303B2

公开(公告)日：2018-04-10

申请号：US14822741

申请日：2015-08-10

Applicant: CloudOn Ltd

Inventor： Shuki Binyamin

IPC: H04L29/08 ,  H04L29/06 ,  G06T1/20 ,  G06F3/0481

CPC classification number: H04L67/025 ,  G06F3/0481 ,  G06T1/20 ,  G06T2200/28 ,  H04L65/60 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/101 ,  H04L67/1021 ,  H04L67/1038 ,  H04L67/16

Abstract: A method of remotely providing an application includes identifying a visible portion of a first application window on a display of a client. A data stream corresponding only to the visible portion of the first application window is received. The received data stream is provided to the client such that the visible portion of the first application window is able to be presented on the display.

公开(公告)号：US09940686B2

公开(公告)日：2018-04-10

申请号：US14277239

申请日：2014-05-14

Applicant: Intel Corporation

Inventor： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/36 ,  G06T15/00 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：US09928567B2

公开(公告)日：2018-03-27

申请号：US15089598

申请日：2016-04-04

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ray Bittner ,  Erik S. Ruf

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F3/14 ,  G06T1/60 ,  G06T2200/28 ,  G09G5/363 ,  G09G2360/06 ,  G09G2360/08

Abstract: A system may include a Graphics Processing Unit (GPU) and a Field Programmable Gate Array (FPGA). The system may further include a bus interface that is external to the FPGA, and that is configured to transfer data directly between the GPU and the FPGA without storing the data in a memory of a central processing unit (CPU) as an intermediary operation.

公开(公告)号：US20180074927A1

公开(公告)日：2018-03-15

申请号：US15658707

申请日：2017-07-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiko MORI

IPC: G06F11/273 ,  G06T1/20 ,  G06F11/22

CPC classification number: G06F11/273 ,  G06F11/2236 ,  G06F11/27 ,  G06T1/20 ,  G06T2200/28

Abstract: A drawing processing device includes a GPU, a diagnosis circuit which executes a diagnostic test of the GPU dividedly and a control unit which controls execution of the divided diagnostic tests by the diagnosis circuit. The control unit schedules so as to complete execution of drawing processes for one frame in a first time which is a one-frame display time which is defined in accordance with a frame rate and schedules so as to execute the divided diagnostic tests in a third time which is a remaining time obtained by subtracting a second time which is a processing time requested for execution of the drawing processes for one frame from the first time.

公开(公告)号：US09906239B1

公开(公告)日：2018-02-27

申请号：US15636306

申请日：2017-06-28

Applicant: ATI Technologies ULC

Inventor： Kyle Plumadore

IPC: H03M7/40 ,  G06T1/20

CPC classification number: H03M7/40 ,  G06T1/20 ,  G06T2200/28

Abstract: Systems, apparatuses, and methods for implementing a parallel Huffman decoding scheme are disclosed herein. A system with a plurality of execution units receives a Huffman encoded bitstream. The system partitions the encoded bitstream into a plurality of chunks. Each execution unit is assigned to decode a separate chunk of the encoded bitstream as well as an extra portion of an adjacent chunk. With this approach, the decoding of the bitstream overlaps for a programmable amount of data at each chunk boundary since each execution unit, excluding the first execution unit decoding the first chunk of the bitstream, will likely decode a certain number of symbols incorrectly at the beginning of the chunk since the chunk boundaries will not be aligned with symbol boundaries. The system determines, from the decoded extra portion at each chunk boundary, where incorrectly decoded ends and where correctly decoded data begins for each decoded chunk.

公开(公告)号：US20180047136A1

公开(公告)日：2018-02-15

申请号：US15793309

申请日：2017-10-25

Applicant: Facebook, Inc.

Inventor： Jonathan M. Kaldor

IPC: G06T3/40 ,  G06T1/60 ,  G06F9/48 ,  G06F3/0481 ,  G06F9/50 ,  G06F3/14 ,  G06T1/20

CPC classification number: G06T3/4092 ,  G06F3/0481 ,  G06F3/14 ,  G06F9/485 ,  G06F9/505 ,  G06F2209/5018 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: In one embodiment, a computing device determines a window of time that is available after each operation to fill a frame buffer. The device determines a first number indicating a number of elements of a requested content that fit into a display region, an increment based on an application-specific rule, and a second number indicating a number of elements to pre-generate based on the first number and the increment. The device selects one or more pre-generation tasks for pre-generating content for the second number of select elements of the requested content. During the window of time, the device executes at least a subset of the pre-generation tasks to pre-generate content for a corresponding subset of the select elements. The pre-generated subset of the select elements is stored in an application-tailored recycler.

公开(公告)号：US09892546B2

公开(公告)日：2018-02-13

申请号：US15013784

申请日：2016-02-02

Applicant: PRIMAL SPACE SYSTEMS, INC.

Inventor： Barry L. Jenkins

IPC: G06T19/00 ,  G06T15/20 ,  G06T15/40

CPC classification number: G06T15/20 ,  G06T15/40 ,  G06T19/003 ,  G06T2200/28 ,  G06T2210/08

Abstract: A method of pursuit path camera model navigation includes, providing, via processing circuitry of one server, a future viewpoint located at a first location and a current viewpoint located at a second location and calculating a first prefetch region including one or more viewcells and one or more visibility even packets, the first prefetch region corresponding to the first location of the future viewpoint and the second location of the current viewpoint. The method further includes receiving commands to modify the first location of the future viewpoint to a third location at a first velocity, calculating a navigational intent of the future viewpoint based on the commands, and calculating a second prefetch region including the viewcells and the visibility event packets by collapsing the calculated first prefetch region into the second prefetch region, the second prefetch region corresponding to a predicted pursuit path based on the calculated navigational intent.

公开(公告)号：US20180040096A1

公开(公告)日：2018-02-08

申请号：US15229550

申请日：2016-08-05

Applicant: Intel IP Corporation

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F13/00 ,  G06F13/1652 ,  G06F13/1657 ,  G06T1/60 ,  G06T2200/28 ,  Y02D10/14

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.