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公开(公告)号:US11823626B2
公开(公告)日:2023-11-21
申请号:US17699943
申请日:2022-03-21
Applicant: Samsung Display Co., Ltd.
Inventor: Jong Hee Kim , Soo Yeon Lee
IPC: G09G3/32 , G09G3/3266 , G09G3/36
CPC classification number: G09G3/3266 , G09G3/3677 , G09G2310/08
Abstract: A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.
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公开(公告)号:US11822197B2
公开(公告)日:2023-11-21
申请号:US17518001
申请日:2021-11-03
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Hajime Kimura
IPC: G09G3/32 , G02F1/1362 , G09G3/20 , G09G3/3233 , G09G3/36 , G11C19/28 , H10K10/46 , G02F1/1335 , G02F1/13363 , H10K10/20
CPC classification number: G02F1/136286 , G02F1/133528 , G09G3/20 , G09G3/3233 , G09G3/3677 , G11C19/28 , H10K10/482 , G02F1/133638 , G09G2300/0408 , G09G2300/0417 , G09G2300/0847 , G09G2310/0254 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291 , G09G2310/08 , G09G2320/043 , H10K10/20
Abstract: To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.
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公开(公告)号:US11816291B2
公开(公告)日:2023-11-14
申请号:US17274920
申请日:2020-06-22
Inventor: Qing Yang , Jiacheng Huang , Gang Zhang , Meng Zhang , Lingling Liu , Tingfei Wang , Qiang Zhu , Yunyun Zhang
IPC: G09G5/00 , G06F3/041 , G02F1/1333 , G02F1/1345 , G09G3/20 , G09G3/32 , G09G3/36 , H10K50/844 , H10K50/86 , H10K59/40 , G02F1/1335
CPC classification number: G06F3/04184 , G02F1/1345 , G02F1/13338 , G06F3/0412 , G09G3/2096 , G09G3/32 , G09G3/3677 , H10K50/844 , H10K50/865 , H10K59/40 , G02F1/133512 , G09G2300/0408 , G09G2300/0426 , G09G2310/0286
Abstract: A timing controller includes: a field programmable gate array configured to generate a reference clock signal, and obtain at least one group of clock signals according to the reference clock signal. Each group of clock signals includes at least two clock signals, and a waveform of each clock signal is same as a waveform of the reference clock signal, and active levels in different clock signals are provided with a delay of a preset duration. The reference clock signal includes a first clock sub-signal for first duration and a second clock sub-signal for a second duration. At least one output interface group is connected to the field programmable gate array. Each output interface group includes at least two output interfaces, and each of the at least two output interfaces is configured to output one clock signal of a group of clock signals corresponding to the output interface group.
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公开(公告)号:US11804274B2
公开(公告)日:2023-10-31
申请号:US18097173
申请日:2023-01-13
Applicant: SHARP KABUSHIKI KAISHA
Inventor: Yoshihisa Takahashi
IPC: G09G3/36 , G11C19/28 , G09G3/20 , G09G3/3266
CPC classification number: G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0223
Abstract: A circuit includes a first transistor whose gate is connected to a set terminal and whose source or drain is connected to an internal node, a second transistor connected such that one of a source and a drain is electrically connected to the internal node and the other one of the source and the drain is electrically connected to a reference voltage source, a third transistor connected such that a gate is connected to the internal node, one of a source and a drain is connected to a clock terminal, and the other one of the source and the drain is connected to a first output terminal, a bootstrap capacitor which is connected to the internal node and the first output terminal, and a stabilization circuit that suppresses a drop in potential at the internal node in a charging period of the bootstrap capacitor.
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公开(公告)号:US11804183B2
公开(公告)日:2023-10-31
申请号:US17587766
申请日:2022-01-28
Applicant: Wuhan Tianma Micro-Electronics Co., Ltd. , Wuhan Tianma MicroElectronics Co., Ltd. Shanghai Branch
Inventor: Mengmeng Zhang , Yue Li , Yuantao Wu , Jing Huang
IPC: G09G3/3266 , G11C19/28 , G09G3/36 , G09G3/20
CPC classification number: G09G3/3266 , G11C19/28 , G09G3/20 , G09G3/3677 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G11C19/287
Abstract: A display panel, a driving method of a display panel, and a display device are provided. The display panel includes pixel circuits and a gate driving circuit including cascaded first shift register units. A trigger signal input terminal of the first stage first shift register unit is connected to a trigger signal terminal through a first switch element. A signal output terminal of the i-th stage first shift register unit is connected to a trigger signal input terminal of the (i+1)-th stage first shift register unit through a second switch element. A trigger signal input terminal of the N-th stage first shift register unit is connected to the trigger signal terminal through a third switch element. A signal output terminal of the j-th stage first shift register unit is connected to a trigger signal input terminal of the (j−1)-th stage first shift register unit through a fourth switch element.
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公开(公告)号:US11798512B1
公开(公告)日:2023-10-24
申请号:US17986129
申请日:2022-11-14
Inventor: Xingru Chen , Changwen Ma , Pengfei Zhang , Zhou Zhang
CPC classification number: G09G3/3677 , G09G3/3607 , G09G3/3688 , G09G2310/0278
Abstract: A display device is provided. The display device inputs a preset gray scale voltage to sub-pixels during a first time period within one frame in a second driving mode, thereby increasing a liquid crystal flipping speed within one frame, and therefore improving a response time of the display device in switching between black screen and white screen.
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公开(公告)号:US11798510B2
公开(公告)日:2023-10-24
申请号:US16981650
申请日:2019-09-11
Inventor: Jiyang Shao , Yuxin Bi , Ziqiang Guo , Bingxin Liu
IPC: G09G3/36 , G09G3/3266 , G09G3/00 , G09G3/32 , G09G3/20
CPC classification number: G09G3/3674 , G09G3/3607 , G09G3/3685 , G09G3/003 , G09G3/20 , G09G3/32 , G09G3/3266 , G09G3/36 , G09G3/3677 , G09G2300/0426 , G09G2310/0221 , G09G2310/0243 , G09G2310/08 , G09G2320/0252 , G09G2320/0626 , G09G2320/0686 , G09G2350/00
Abstract: A display apparatus includes a display panel and a gate driving circuit. A display area of the display panel includes at least two sub-display areas, and each sub-display area of the at least two sub-display areas includes a plurality of sub-pixels. The gate driving circuit includes at least two gate driving sub-circuits in one-to-one correspondence with the at least two sub-display areas, and each gate driving sub-circuit of the at least two gate driving sub-circuits is electrically connected to a plurality of sub-pixels included in a corresponding sub-display area. Each gate driving sub-circuit is configured to receive a group of first control signals, generate a group of gate driving signals according to the group of first control signals, and output the group of gate driving signals to the plurality of sub-pixels included in the corresponding sub-display area.
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公开(公告)号:US11798509B2
公开(公告)日:2023-10-24
申请号:US17602243
申请日:2020-04-10
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Hiroyoshi Ichikura
CPC classification number: G09G3/3648 , G09G3/20 , G09G3/3677 , G09G3/3688 , G09G2310/0275 , G09G2310/0297 , G09G2310/08
Abstract: A display driver drives a display device including a plurality of data lines and a demultiplexer. The demultiplexer includes a plurality of first switches connected to the respective plurality of data lines, and a series of driving voltages including a plurality of driving voltages is supplied via a first wiring. The demultiplexer supplies the plurality of driving voltages to the respective plurality of data lines via the plurality of first switches. The display driver includes: a voltage multiplexing part that generates the series of driving voltages; a second switch connected between the voltage multiplexing part and the first wiring; and a controller connected to the plurality of first switches and the second switch. The controller switches the second switch from an on state to an off state during a first period and sets the two first switches corresponding to the two data lines to the on state such that the two data lines and the first wiring are connected during a second period that is a part of the first period and in which the second switch is in the off state.
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公开(公告)号:US20230326413A1
公开(公告)日:2023-10-12
申请号:US18211548
申请日:2023-06-19
Applicant: Samsung Display Co., Ltd.
Inventor: Hai Jung IN , Soon Gi KWON
IPC: G09G3/3266 , G09G3/3233 , G09G3/36
CPC classification number: G09G3/3266 , G09G3/3233 , G09G3/3677 , G09G2310/08 , G09G2310/0286
Abstract: A scan driver and a driving method thereof, in which the scan driver includes a plurality of stages outputting an output signal in response to clock signals supplied at a first frequency during a driving time of one frame, wherein the plurality of stages are supplied with the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame.
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公开(公告)号:US20230317190A1
公开(公告)日:2023-10-05
申请号:US18205000
申请日:2023-06-02
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Atsushi UMEZAKI
CPC classification number: G11C19/184 , G09G3/3677 , G09G3/3648 , G09G3/3266
Abstract: In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.
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