Integrated clock generator and timing/frequency reference
    52.
    发明授权
    Integrated clock generator and timing/frequency reference 有权
    集成时钟发生器和定时/频率参考

    公开(公告)号:US07656245B2

    公开(公告)日:2010-02-02

    申请号:US12036185

    申请日:2008-02-22

    IPC分类号: H03B5/12

    摘要: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

    摘要翻译: 在各种实施例中,本发明提供使用LC振荡器拓扑的时钟发生器和/或定时和频率参考,其具有频率控制器以控制和提供稳定的谐振频率,其与其它第二电路(例如处理器 或控制器。 提供了频率稳定性,如选择的参数(如温度和制造工艺变化)的变化。 各种装置实施例包括适于响应于多个参数的至少一个参数提供信号的传感器; 以及频率控制器,其适于响应于所述第二信号来修改所述谐振频率。 在示例性实施例中,响应于温度波动将传感器实现为电流源,并且频率控制器被实现为可选择地耦合到谐振器或一个或多个控制电压的多个受控电抗模块。 受控电抗模块可以包括固定或可变电容或电感,并且可以是二进制加权的。 还提供了电阻模块的阵列,以产生一个或多个控制电压。

    Low power consumption frequency divider circuit
    53.
    发明授权
    Low power consumption frequency divider circuit 失效
    低功耗分频电路

    公开(公告)号:US07446617B2

    公开(公告)日:2008-11-04

    申请号:US11606071

    申请日:2006-11-30

    IPC分类号: H03B5/12 H03L7/24

    摘要: The present invention discloses a low power consumption frequency divider circuit. It mainly comprises a signal source; a signal injection circuit; and an oscillator circuit. The low-power consumption frequency divider circuit according to the present invention mainly uses the configuration of current reused circuit to form the common current path for reducing the power loss in the disclosed frequency divider circuit.

    摘要翻译: 本发明公开了一种低功耗分频电路。 它主要包括信号源; 信号注入电路; 和振荡电路。 根据本发明的低功耗分频器电路主要使用电流重用电路的配置来形成用于降低所公开的分频器电路中的功率损耗的公共电流路径。

    Vco Device, and Tuner, Broadcast Receiver and Mobile Telephone Using the Same
    55.
    发明申请
    Vco Device, and Tuner, Broadcast Receiver and Mobile Telephone Using the Same 审中-公开
    Vco设备和调谐器,广播接收机和使用相同的移动电话

    公开(公告)号:US20080068098A1

    公开(公告)日:2008-03-20

    申请号:US11629695

    申请日:2006-01-30

    IPC分类号: H03B21/01

    摘要: It is intended to provide a VCO apparatus having: a local oscillation signal generation circuit for outputting a local oscillation signal corresponding to a frequency signal of a tuned channel to be received, the frequency signal being included in high frequency signals received by an input terminal, and a mixing circuit for outputting a baseband signal by mixing the high frequency signal and the local oscillation signal, wherein the local oscillation signal generation circuit has an oscillator for oscillating the local oscillation signal and a frequency reduction unit for outputting a frequency of the local oscillation signal oscillated by the oscillator to the mixing circuit at a ratio of ×1/N, and the local oscillation signal frequency is set to a frequency different from a communication wireless frequency used by a mobile phone by adjusting the ratio of ×1/N.

    摘要翻译: 本发明旨在提供一种VCO装置,其具有本地振荡信号生成电路,用于输出对应于要接收的调谐信道的频率信号的本地振荡信号,所述频率信号包含在由输入端子接收的高频信号中, 以及混合电路,用于通过混合高频信号和本地振荡信号来输出基带信号,其中本地振荡信号产生电路具有用于振荡本地振荡信号的振荡器和用于输出本地振荡频率的频率降低单元 信号以x1 / N的比例由振荡器振荡到混合电路,并且通过调整x1 / N的比率将本地振荡信号频率设置为与移动电话使用的通信无线频率不同的频率。

    Integrated clock generator and timing/frequency reference
    57.
    发明申请
    Integrated clock generator and timing/frequency reference 有权
    集成时钟发生器和定时/频率参考

    公开(公告)号:US20060152293A1

    公开(公告)日:2006-07-13

    申请号:US11384758

    申请日:2006-03-20

    IPC分类号: H03B1/00

    摘要: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

    摘要翻译: 在各种实施例中,本发明提供使用LC振荡器拓扑的时钟发生器和/或定时和频率参考,其具有频率控制器以控制和提供稳定的谐振频率,其与其它第二电路(例如处理器 或控制器。 提供了频率稳定性,如选择的参数(如温度和制造工艺变化)的变化。 各种装置实施例包括适于响应于多个参数的至少一个参数提供信号的传感器; 以及频率控制器,其适于响应于所述第二信号来修改所述谐振频率。 在示例性实施例中,响应于温度波动将传感器实现为电流源,并且频率控制器被实现为可选择地耦合到谐振器或一个或多个控制电压的多个受控电抗模块。 受控电抗模块可以包括固定或可变电容或电感,并且可以是二进制加权的。 还提供了电阻模块的阵列,以产生一个或多个控制电压。

    Oscillator Topology for Very Low Phase Noise Operation
    59.
    发明申请
    Oscillator Topology for Very Low Phase Noise Operation 失效
    非常低相位噪声运算的振荡器拓扑

    公开(公告)号:US20040108908A1

    公开(公告)日:2004-06-10

    申请号:US10605635

    申请日:2003-10-15

    申请人: RF MAGIC, INC.

    IPC分类号: H03B001/00

    摘要: An oscillator circuit includes a tank circuit, first and second oscillator transistors, and a gain-cell tuning inductor. The tank circuit includes first and second ports, and is configured to resonate at one or more predefined frequencies. The first oscillator transistor includes first port, a second port coupled to the first port of the tank circuit, and a third port. The second oscillator transistor includes a first port, a second port coupled to the second port of the tank circuit, and a third port. The gain-cell tuning inductor is coupled between the third ports of the first and second oscillator transistors and is operable to conduct a biasing signal supplied thereto to the third ports of the first and second oscillator transistors.

    摘要翻译: 振荡电路包括一个振荡电路,一个和第二个振荡晶体管,以及一个增益单元调谐电感。 储能电路包括第一和第二端口,并且被配置为以一个或多个预定频率谐振。 第一振荡器晶体管包括第一端口,耦合到储能电路的第一端口的第二端口和第三端口。 第二振荡器晶体管包括第一端口,耦合到储能电路的第二端口的第二端口和第三端口。 增益单元调谐电感器耦合在第一和第二振荡晶体管的第三端口之间,并且可操作地将提供给其的偏置信号传导到第一和第二振荡晶体管的第三端口。

    Oscillator circuit
    60.
    发明授权

    公开(公告)号:US06606008B2

    公开(公告)日:2003-08-12

    申请号:US09991790

    申请日:2001-11-19

    申请人: Johann Traub

    发明人: Johann Traub

    IPC分类号: H03B500

    摘要: An oscillator circuit is described and has an oscillator core with at least one inductance and, connected thereto, a first and second capacitance. A deattenuator is coupled to the oscillator core and has two transistors, which are cross-coupled to one another in a non-direct-electrical coupling. The respective load terminal of a respective transistor is directly connected to a reference-ground potential terminal. The non-direct-electrical, for example inductive, coupling of the transistors in combination with the transistors directly connected to ground enables a greater modulation capability and also a smaller phase noise of the oscillator circuit. In this case, the transistors are operated as current switches. In preferred embodiments, the oscillator circuit has a regulating circuit for a bias voltage and an operating-current setting. The present oscillator circuit is suitable for mobile radio applications with stringent phase noise requirements in the gigahertz range and can be integrated into CMOS circuit technology.