公开(公告)号：US08723552B2

公开(公告)日：2014-05-13

申请号：US13413325

申请日：2012-03-06

申请人： Pei-Kai Tseng ,  Chien-Fu Tang ,  Kuang-Feng Li ,  Isaac Y. Chen

发明人： Pei-Kai Tseng ,  Chien-Fu Tang ,  Kuang-Feng Li ,  Isaac Y. Chen

IPC分类号： H03K19/0175 ,  G05F1/00

CPC分类号： H03K19/018507 ,  H03K19/00361

摘要： A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node.

摘要翻译： 浮置栅极驱动器电路包括电平移位器，通过元件，双稳态电路和控制逻辑电路，以将控制信号的电压电平从较低的一个移动到较高的一个。 电平移位器或通过元件具有由控制逻辑电路动态控制的负载，以过滤由浮动节点引起的dv / dt噪声引起的故障。

公开(公告)号：US08717076B1

公开(公告)日：2014-05-06

申请号：US13754543

申请日：2013-01-30

申请人： Texas Instruments Incorporated

发明人： Adam L. Shook

IPC分类号： H03K5/12

CPC分类号： H03K19/00361 ,  G05F3/16 ,  H03K5/12 ,  H03K19/00384

摘要： An apparatus, comprising: a PMOS current mirror have a first PFET and a second PFET coupled at their respective gates; a first current source coupled to drain of the first PFET; a second current source configured to have a current that is greater than the first current source, coupled to the drain of the second PFET; a capacitor coupled to the gates of the PFET current mirror; a third PFET gate-coupled to the current mirror; a driver NFET having a gate coupled to the drain of the third PFET, wherein a drain of the driver NFET is coupled to the capacitor.

摘要翻译： 一种装置，包括：PMOS电流镜，具有在其各自的栅极耦合的第一PFET和第二PFET; 耦合到所述第一PFET的漏极的第一电流源; 被配置为具有大于所述第一电流源的电流的第二电流源，耦合到所述第二PFET的漏极; 耦合到PFET电流镜的栅极的电容器; 栅极耦合到电流镜的第三PFET; 具有耦合到第三PFET的漏极的栅极的驱动器NFET，其中驱动器NFET的漏极耦合到电容器。

公开(公告)号：US20140103965A1

公开(公告)日：2014-04-17

申请号：US14107052

申请日：2013-12-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  GLOBAL UNICHIP CORPORATION

发明人： Wen-Tai Wang ,  Chao-Yen Huang

IPC分类号： H03K17/081

CPC分类号： H03K17/08104 ,  H03K19/00315 ,  H03K19/00361

摘要： A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

摘要翻译： 两级后驱动电路包括控制电路，上拉单元和下拉单元。 下拉单元的第一N型晶体管和上拉单元的第一P型晶体管都连接到输出焊盘。 控制电路用于控制第一N型晶体管和第一P型晶体管。 因此，当上拉单元或下拉单元接通时，第一N型晶体管或第一P型晶体管的漏极端子和源极端子之间的电压差低于电压应力。

公开(公告)号：US08674742B2

公开(公告)日：2014-03-18

申请号：US13538724

申请日：2012-06-29

申请人： Atsuya Ohashi ,  Koji Kimura

发明人： Atsuya Ohashi ,  Koji Kimura

IPC分类号： H03L5/00 ,  H03K5/08

CPC分类号： H03K19/00361

摘要： A second driver is provided in addition to a first driver outputting an output signal in accordance with a voltage of an input signal. When the output signal changes from a first voltage level to a second voltage level in accordance with a voltage change of the input signal, a control part controls the second driver to assist the signal change during a period from a change start time until the output signal exceeds a third voltage level. The control part controls the second driver to suppress the signal change during a period from the time when the output signal exceeds the third voltage level until it reaches the second voltage level.

摘要翻译： 除了第一驱动器之外还提供了第二驱动器，该第一驱动器根据输入信号的电压输出输出信号。 当输出信号根据输入信号的电压变化从第一电压电平变化到第二电压电平时，控制部分控制第二驱动器以在从改变开始时间直到输出信号的一段时间内辅助信号改变 超过第三电压电平。 控制部控制第二驱动器，以抑制从输出信号超过第三电压电平直到达到第二电压电平的期间的信号变化。

公开(公告)号：US20140049306A1

公开(公告)日：2014-02-20

申请号：US13719016

申请日：2012-12-18

申请人： SK HYNIX INC.

发明人： Kwan Su SHON

IPC分类号： H03H11/26

CPC分类号： H03H11/26 ,  H03K19/00361

摘要： A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time.

摘要翻译： 信号传输电路包括预驱动器和驱动器。 预驱动器被配置为响应于第一延迟信号和第一选择信号而产生第一驱动信号，并响应于第二延迟信号，第二选择信号和脉冲信号产生第二驱动信号。 驱动器被配置为响应于第一和第二驱动信号来驱动发送信号。 第一延迟信号在比接收到输入信号的第一时间晚的第二时间使能，第二延迟信号在晚于第二时间的第三时间被使能，并且脉冲信号在一个 第四次从第一次延迟预定的延迟时间。

公开(公告)号：US08638131B2

公开(公告)日：2014-01-28

申请号：US13032808

申请日：2011-02-23

申请人： Wilson J. Chen ,  Chiew-Guan Tan

发明人： Wilson J. Chen ,  Chiew-Guan Tan

IPC分类号： H03K3/00

CPC分类号： H03K19/00361 ,  H03K17/163 ,  H03K19/018507

摘要： In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.

摘要翻译： 在示例中，提供了减轻由于输出电容负载，制造工艺，电压和/或温度（PVT）的变化引起的缓冲器压摆率变化的装置和方法。 示例性实施例包括具有输入和输出的反相缓冲器，以及与输入和输出之间的电容器串联耦合的有源电阻。 有源电阻的电阻根据制造工艺，电压和/或温度的变化而变化。 主动阻力可以是通道。 在另一示例中，CMOS反相器的输出耦合到反相缓冲器的输入，并且两个串联耦合的反相缓冲器耦合在CMOS反相器的输入端和反相缓冲器的输出端之间。

公开(公告)号：US20140009133A1

公开(公告)日：2014-01-09

申请号：US13774817

申请日：2013-02-22

申请人： FINISAR CORPORATION

发明人： Georgios KALOGERAKIS ,  Jason Y. MIAO ,  The'linh NGUYEN

IPC分类号： G05F1/625

CPC分类号： G05F1/625 ,  H03K19/00361 ,  H03K19/017509 ,  H03K19/017527

摘要： A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage. The circuit may also include a tap circuit configured to selectively apply a modified version of the signal to the signal driven by the second circuit before the signal driven by the second circuit reaches the active device.

摘要翻译： 电路可以包括被配置为接收信号的输入节点和被配置为耦合到负载的输出节点。 电路还可以包括耦合在输入节点和输出节点之间的第一电路。 第一电路可以被配置为接收信号并以第一电压驱动输出节点上的信号。 电路还可以包括耦合到输出节点的有源器件和耦合到有源器件和输入节点的第二电路。 第二电路可以被配置为接收信号并且以第二电压将信号驱动到有源器件。 电路还可以包括抽头电路，其被配置为在由第二电路驱动的信号到达有源器件之前，将信号的修改版本选择性地应用于由第二电路驱动的信号。

公开(公告)号：US08558520B2

公开(公告)日：2013-10-15

申请号：US13120874

申请日：2008-09-30

申请人： Alexis Huot-Marchand ,  Hamada Ahmed ,  Patrice Besse ,  Nicolas Jarrige

发明人： Alexis Huot-Marchand ,  Hamada Ahmed ,  Patrice Besse ,  Nicolas Jarrige

IPC分类号： G05F1/00 ,  H02H3/20 ,  H02H9/04 ,  H02H7/122

CPC分类号： H03K17/167 ,  H03K17/0822 ,  H03K19/00361

摘要： An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage.

摘要翻译： 用于操纵总线上的电压和电流中的至少一个的电路包括具有第一栅极，第一源极和第一电位降低单元的第一开关。 第一电位降低单元适于降低第一开关的第一栅极和第一源极之间的电位差，其中电位差的降低是由第一控制电压的关断引起的。

公开(公告)号：US20130254434A1

公开(公告)日：2013-09-26

申请号：US13901140

申请日：2013-05-23

申请人： FUJITSU LIMITED

发明人： Masaki Fujioka ,  Koji Migita ,  Kazumasa Kubotera ,  Yasutaka Kanayama

IPC分类号： H03K17/16

CPC分类号： H03K17/16 ,  H03K5/1252 ,  H03K19/00361

摘要： A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

摘要翻译： 包括用于接收输入信号的输入端子和用于输出输出信号的输出端子的半导体器件包括与输入端子串联连接的延迟元件，并且每个延迟元件将延迟分配给从输入端子输入的输入信号，连接到 延迟元件的输出侧，并且每个用于基于用于选择延迟元件的输出信号中的一个的选择信号来选择延迟元件的输出信号之一，以将输出信号中选择的一个输出信号返回到输出端子;以及 延迟电路，其对应于选择器设置，并且每个用于使输入的选择信号的切换输入到相应的一个选择器中，以在切换输入到用作信号转折点的相应选择器中的相应一个的输入信号的信号电平之后发生 。

公开(公告)号：US08482323B2

公开(公告)日：2013-07-09

申请号：US13089253

申请日：2011-04-18

申请人： Masatomo Eimitsu ,  Takanori Saeki

发明人： Masatomo Eimitsu ,  Takanori Saeki

IPC分类号： H03B1/00

CPC分类号： H03K19/00361 ,  H03K17/162 ,  H03K19/00384 ,  H03K19/0948

摘要： A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.