公开(公告)号：US20130121341A1

公开(公告)日：2013-05-16

申请号：US13732198

申请日：2012-12-31

Applicant: JUNIPER NETWORKS, INC.

Inventor： Anurag AGRAWAL ,  Philip A. THOMAS

IPC: H04L12/56

CPC classification number: H04L47/522 ,  H04L49/9047 ,  H04L49/9089

Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract translation: 网络设备包括主存储存储器和队列处理组件。 主存储器包括存储用于多个输出队列的多个分组的多个存储体。 队列处理组件控制对多个存储体的写入操作并控制来自多个存储体的读取操作，其中多个输出队列中的至少一个的读取操作在多个存储器组中的每一个之间顺序地交替，并且读取 操作和写入操作在多个存储体中的不同存储体上的同一时钟周期内发生。

公开(公告)号：US08386626B2

公开(公告)日：2013-02-26

申请号：US13168403

申请日：2011-06-24

Applicant: Anil Vasudevan ,  Sujoy Sen ,  Partha Sarangam

Inventor： Anil Vasudevan ,  Sujoy Sen ,  Partha Sarangam

IPC: G06F15/16 ,  H04J3/00 ,  G06F3/00

CPC classification number: H04L47/622 ,  H04L47/2475 ,  H04L49/90 ,  H04L49/9047 ,  H04L49/9063 ,  H04L49/9094 ,  H04L69/12 ,  H04L69/32

Abstract: According to some embodiments, it may be determined, at a first processing element of a device with a plurality of processing elements, that first data is to be transmitted in association with a first network connection. A first entry associated with the first data may then be stored into a first of a plurality of transmit queues. It may subsequently be determined, at a second processing element of the device, that second data is to be transmitted in association with the first network connection. A second entry associated with the second data may then be stored into a second of the plurality of transmit queues.

Abstract translation: 根据一些实施例，可以在具有多个处理元件的设备的第一处理元件处确定要与第一网络连接相关联地发送第一数据。 然后可以将与第一数据相关联的第一条目存储在多个发送队列中的第一个中。 随后可以在设备的第二处理元件处确定与第一网络连接相关联地发送第二数据。 然后可以将与第二数据相关联的第二条目存储到多个发送队列中的第二条目中。

公开(公告)号：US20120033680A1

公开(公告)日：2012-02-09

申请号：US13208093

申请日：2011-08-11

Applicant: Sandhya Gopinath ,  Henk Bots

Inventor： Sandhya Gopinath ,  Henk Bots

IPC: H04L12/56

CPC classification number: H04L49/901 ,  H04L49/9047 ,  H04L49/9057

Abstract: Described herein is a method and system for directing outgoing data packets from packet engines to a transmit queue of a NIC in a multi-core system, and a method and system for directing incoming data packets from a receive queue of the NIC to the packet engines. Packet engines store outgoing traffic in logical transmit queues in the packet engines. An interface module obtains the outgoing traffic and stores it in a transmit queue of the NIC, after which the NIC transmits the traffic from the multi-core system over a network. The NIC receives incoming traffic and stores it in a NIC receive queue. The interface module obtains the incoming traffic and applies a hash to a tuple of each obtained data packet. The interface module then stores each data packet in the logical receive queue of a packet engine on the core identified by the result of the hash.

Abstract translation: 这里描述的是用于将来自分组引擎的输出数据分组引导到多核系统中的NIC的发送队列的方法和系统，以及用于将来自NIC的接收队列的输入数据分组引导到分组引擎的方法和系统 。 分组引擎将传出流量存储在分组引擎中的逻辑传输队列中。 接口模块获取传出流量并将其存储在NIC的传输队列中，NIC之后通过网络从多核系统传输流量。 NIC接收传入流量并将其存储在NIC接收队列中。 接口模块获取输入流量，并将散列应用于每个获得的数据包的元组。 接口模块然后将每个数据包存储在由散列结果标识的核上的分组引擎的逻辑接收队列中。

公开(公告)号：US08098674B2

公开(公告)日：2012-01-17

申请号：US11362522

申请日：2006-02-27

Applicant: Mami Sekido ,  Akihiro Hata ,  Satoshi Nishimura ,  Yuuji Kubo

Inventor： Mami Sekido ,  Akihiro Hata ,  Satoshi Nishimura ,  Yuuji Kubo

IPC: H04L12/28

CPC classification number: H04L49/90 ,  H04L47/50 ,  H04L47/60 ,  H04L49/9047

Abstract: A queue selection method for controlling selection of many queues without increasing the circuit scale is provided. Queues are organized into groups, and each group is created as a tree structure with a plurality of steps, and a queue is selected by selecting a group of each step. By this, even if the number of queues is enormous, it is sufficient to provide registers for managing the presence of packets only for the number of groups selected in each step, and it becomes unnecessary to provide registers for all of the queues, so an increase of registers can be suppressed even if the number of queues increases. It is preferable that group selection in each step is performed in parallel independently from pipeline processing so as to maintain high-speed operation.

Abstract translation: 提供了一种用于在不增加电路规模的情况下控制许多队列的选择的队列选择方法。 队列被组织成组，并且每个组被创建为具有多个步骤的树结构，并且通过选择每个步骤的组来选择队列。 由此，即使队列数量庞大，仅仅为每个步骤中选择的组数量提供用于管理数据包存在的寄存器就足够了，因此不必为所有队列提供寄存器，因此， 即使队列数量增加，也可以抑制寄存器的增加。 优选地，独立于流水线处理并行地执行每个步骤中的组选择，以便保持高速操作。

公开(公告)号：US08090896B2

公开(公告)日：2012-01-03

申请号：US12217333

申请日：2008-07-03

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: G06F12/00

CPC classification number: H04L49/901 ,  G06F9/345 ,  G06F9/3885 ,  G06F12/0607 ,  H03M13/276 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/6505 ,  H03M13/6566 ,  H04L47/14 ,  H04L49/90 ,  H04L49/9047 ,  Y02D10/13

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract translation: 存储体具有多个存储器。 在一个实施例中，前向单元以前向双向访问顺序将逻辑存储器地址应用于存储体，后向单元以向后双向访问顺序向存储体提供逻辑存储器地址，以及半蝶形网络（至少一半， 和8元组实施例中的桶形移位器）被布置在存储体和前向单元和后向单元之间。 生成一组控制信号，这些控制信号被施加到一半或更多个蝶形网络（以及当前的桶形移位器），以便在第一种情况下以线性顺序访问具有n元组并行性的存储体， 二次多项式次序，其中n = 2，4，8，16，32，...。 。 。 。 该访问用于逻辑地址的任何n元组，并且没有内存访问冲突。 以这种方式，存储器访问可以被控制数据解码。

公开(公告)号：US08077724B2

公开(公告)日：2011-12-13

申请号：US12856386

申请日：2010-08-13

Applicant: Rasoul Mirzazadeh Oskouy ,  Dennis C Ferguson ,  Hann-Hwan Ju ,  Raymond Marcelino Manese Lim ,  Pradeep S Sindhu ,  Sreeram Veeragandham ,  Jeff Zimmer ,  Michael M. Y. Hui

Inventor： Rasoul Mirzazadeh Oskouy ,  Dennis C Ferguson ,  Hann-Hwan Ju ,  Raymond Marcelino Manese Lim ,  Pradeep S Sindhu ,  Sreeram Veeragandham ,  Jeff Zimmer ,  Michael M. Y. Hui

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L45/74 ,  G06F11/08 ,  H04L1/0041 ,  H04L12/56 ,  H04L12/5601 ,  H04L29/06 ,  H04L45/00 ,  H04L45/20 ,  H04L45/60 ,  H04L47/6225 ,  H04L49/103 ,  H04L49/108 ,  H04L49/203 ,  H04L49/25 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3063 ,  H04L49/3081 ,  H04L49/555 ,  H04L49/602 ,  H04L49/608 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L69/16 ,  H04L69/161 ,  H04L69/22 ,  H04L69/324 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04Q11/0478

Abstract: A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

Abstract translation: 一种用于在通过包括路由器的网络在源和目的地之间传输数据分组的系统中的路由器路由数据包的同时处理数据分组的方法和装置。 该方法包括在接收到数据分组并且将数据分组的任何部分传送到分组存储器之前接收数据分组和数据分组的预处理层报头数据。 数据分组此后被存储在分组存储器中。 确定通过路由器的路由，其包括描述网络中的下一个连接的下一跳索引。 从分组存储器检索数据分组，并且在从存储器检索数据分组的同时，从下一跳索引构建数据分组的新层头。 在从路由器传送之前，将新层标头耦合到数据包。

公开(公告)号：US07996604B1

公开(公告)日：2011-08-09

申请号：US11258682

申请日：2005-10-25

Applicant: Gautam Nag Kavipurapu ,  Sweatha Rao ,  Chris Althouse

Inventor： Gautam Nag Kavipurapu ,  Sweatha Rao ,  Chris Althouse

IPC: G06F5/08

CPC classification number: H04L49/9047 ,  H04L47/6215 ,  H04L49/90 ,  H04L49/901

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract translation: 提供共享存储器开关用于存储和检索来自PLD的BlockRAM（BRAM）存储器的数据。 一组类队列基于BRAM中的存储时间来维护一组指针，其中显示存储在交换机中的存储器中的传入“单元”或“数据包”的位置。 实现了非阻塞存储器架构，其允许创建可扩展的N×N存储器结构（N =输入和输出端口的数量）。 写控制器将数据跨越该N×N存储器，以防止在读入或读出数据时发生数据冲突。 数据被安排为基于类队列中的优先级或类别从该N×N共享存储器缓冲器读出，优先级由用户设置，然后从BRAM中读出数据。

公开(公告)号：US20110158249A1

公开(公告)日：2011-06-30

申请号：US12650080

申请日：2009-12-30

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Fabrice J. Verplanken ,  Colin B. Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC: H04L12/56

CPC classification number: H04L49/9047

Abstract: An assignment constraint matrix method and apparatus used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.

Abstract translation: 一种分配约束矩阵方法和装置，用于从网络处理设备中的多个源（诸如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器。 分配约束矩阵被实现为适于同时并行操作的多个限定符矩阵。 多个限定符矩阵中的每一个适于确定被支持的源的子集中的源，所述源被限定为基于分配约束向一组接收器提供工作。 合格来源的确定可以是可以在单个芯片上提供用于一组接收器或分布在多个芯片上的接收器可用性信息。

公开(公告)号：US20110110383A1

公开(公告)日：2011-05-12

申请号：US12942677

申请日：2010-11-09

Applicant: Kuo-Nan YANG ,  Yen-Hsu Shih ,  Chia-Ying Chiu ,  Kai-Wen Cheng

Inventor： Kuo-Nan YANG ,  Yen-Hsu Shih ,  Chia-Ying Chiu ,  Kai-Wen Cheng

IPC: H04L12/66

CPC classification number: H04L49/9078 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9057

Abstract: The disclosure is a network interface controller (NIC) capable of sharing buffers, which is coupled to a host and a network to make the network connection. The NIC includes a transmitting buffer, a transmitting controller, a receiving buffer, and a receiving controller. The transmitting controller controls the transmitting buffer to transmit the transmission data provided by the host to the network. The receiving controller controls the receiving buffer to transmit the reception data received from the network to the host, and determines a storage capacity of the receiving buffer. When the storage capacity is smaller than a set value, the receiving controller transmits a request signal to the transmitting controller, the transmitting controller generates a response signal according to the request signal and a status signal corresponding to the transmitting buffer, and the receiving controller controls whether reception data is stored in the transmitting buffer according to the response signal.

Abstract translation: 本公开是能够共享缓冲器的网络接口控制器（NIC），其耦合到主机和网络以进行网络连接。 NIC包括发送缓冲器，发送控制器，接收缓冲器和接收控制器。 发送控制器控制发送缓冲器将由主机提供的发送数据发送到网络。 接收控制器控制接收缓冲器将从网络接收的接收数据发送到主机，并确定接收缓冲器的存储容量。 当存储容量小于设定值时，接收控制器向发送控制器发送请求信号，发送控制器根据请求信号和对应于发送缓冲器的状态信号生成响应信号，接收控制器控制 接收数据是否根据响应信号存储在发送缓冲器中。

公开(公告)号：US20110010607A1

公开(公告)日：2011-01-13

申请号：US12500475

申请日：2009-07-09

Applicant: Vijayalakshmi R. RAVEENDRAN

Inventor： Vijayalakshmi R. RAVEENDRAN

IPC: H03M13/09

CPC classification number: H04W4/00 ,  H04L1/0065 ,  H04L1/0067 ,  H04L1/007 ,  H04L47/14 ,  H04L47/20 ,  H04L47/38 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L65/605 ,  H04L69/08 ,  H04W28/06

Abstract: A method of transmitting content to a wireless display device is disclosed. The method may include receiving multimedia data, encoding the multimedia data, and writing encoded multimedia data into a first predetermined memory location of a shared memory. Further, the method may include encapsulating the encoded multimedia data and writing encapsulation data into a second predetermined memory location of the shared memory. The method may also include calculating error control encoding and writing the error control encoding into a third predetermined memory location of the shared memory. Further, the method may include transmitting the encoded multimedia data, the encapsulation data, and the error control encoding to the wireless display device.

Abstract translation: 公开了一种向无线显示设备发送内容的方法。 该方法可以包括接收多媒体数据，对多媒体数据进行编码，以及将编码的多媒体数据写入共享存储器的第一预定存储器位置。 此外，该方法可以包括封装编码的多媒体数据并将封装数据写入共享存储器的第二预定存储器位置。 该方法还可以包括计算错误控制编码和将错误控制编码写入共享存储器的第三预定存储器位置。 此外，该方法可以包括向无线显示设备发送编码的多媒体数据，封装数据和错误控制编码。