公开(公告)号：US20100126825A1

公开(公告)日：2010-05-27

申请号：US12593200

申请日：2008-03-28

Applicant: Esko Nieminen ,  Markku Santala

Inventor： Esko Nieminen ,  Markku Santala

IPC: B65G47/46

CPC classification number: B65G1/08 ,  B65G47/266 ,  B65G2201/0232

Abstract: A sorting deck for paper, board, or pulp rolls has a plane (1) for transporting the rolls and controllable stops (2) for holding the rolls in place and releasing them. The stops (2) are positioned to form at least one line (3) in placed consecutively in the longitudinal direction (4) of the plane (1), and at least one row (5), in which the stops (2) are positioned adjacently to each other along the lateral direction (6) of the plane (1). At least some of the stops (2) are a collector (41) and a feeder (42), both of which can be moved freely between the hold and release positions, so that the travel of the rolls over the stop (2) can be optionally prevented, freely permitted, or permitted one roll at a time. The same sorting deck can be used to handle rolls of different widths.

Abstract translation: 用于纸张，纸板或纸浆辊的分拣板具有用于输送辊的平面（1）和用于将辊保持在适当位置并将其释放的可控制止挡（2）。 止动件（2）定位成形成在平面（1）的纵向方向上连续放置的至少一条线（3），以及至少一排（5），其中止动件（2） 沿着平面（1）的横向（6）彼此相邻地定位。 至少一些止动件（2）是收集器（41）和进料器（42），两者都可以在保持和释放位置之间自由移动，使得辊子在止动件（2）上的行进可以 一次可选地防止，自由允许或允许一卷。 相同的分拣台可用于处理不同宽度的卷。

公开(公告)号：US20050097431A1

公开(公告)日：2005-05-05

申请号：US10696926

申请日：2003-10-30

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: H03M13/03 ,  H03M13/29 ,  H04L1/00 ,  H04L1/20

CPC classification number: H04L1/005 ,  H03M13/2957 ,  H04L1/0066 ,  H04L1/20

Abstract: In one aspect this invention provides a method to operate a decoder, and a decoder that operates in accordance with the method. The method includes monitoring, during operation of the decoder on a signal received from a channel, the value of at least one extrinsic value; and based on the monitored at least one value, determining whether the signal comprises a valid code word or comprises only noise. In a preferred, but non-limiting embodiment, the decoder comprises one of a LogMap or a MaxLogMap turbo decoder, and the decoder forms a part of a baseband section of a wideband code division multiple access (WCDMA) user equipment. During the process of decoding rounds the absolute values of extrinsic values tend to increase, provided that the input signal contains a valid code word, as opposed to when the input signal contains only noise, and where determining accurately distinguishes a valid code word from noise, and may also obtain information that is indicative of the quality of the decoding process.

Abstract translation: 一方面，本发明提供一种操作解码器的方法，以及根据该方法操作的解码器。 该方法包括：在从解码器接收的信号的操作期间监视至少一个外在值的值; 并且基于所监视的至少一个值，确定所述信号是包括有效码字还是仅包括噪声。 在优选但非限制性实施例中，解码器包括LogMap或MaxLogMap turbo解码器之一，并且解码器形成宽带码分多址（WCDMA）用户设备的基带部分的一部分。 在解码过程中，如果输入信号包含有效码字，与输入信号仅包含噪声相反，并且在确定准确区分有效码字和噪声的情况下，外部值的绝对值趋于增加， 并且还可以获得指示解码处理的质量的信息。

公开(公告)号：US06453808B1

公开(公告)日：2002-09-24

申请号：US09622303

申请日：2000-08-15

Applicant: Esko Nieminen ,  Pertti Aimonen

Inventor： Esko Nieminen ,  Pertti Aimonen

IPC: B41F1716

CPC classification number: B65H35/02 ,  B65H18/28 ,  B65H2511/40 ,  D06H1/00 ,  G06K1/121 ,  Y10S414/124 ,  B65H2220/02

Abstract: A method and apparatus for automatically marking paper, board or cellulose web rolls at a slitter for the purpose of identifying the rolls during later finishing steps. Such finishing operations include, e.g., roll transport, rewinding, sheeting or other finishing steps and roll packaging. The roll identification code is also used for material management related to customer rolls. The roll identification information of a roll set leaving the slitter, that is, the sequence of rolls exiting from the slitter as a group is transmitted for the use of the roll marking equipment and the customer rolls are moved away from the slitter area only via the roll marking equipment and new rolls are prevented from entering the slitter area in any other form except as a new roll set. As a result, the correct identification data for each roll set is continuously available to the marking equipment.

Abstract translation: 一种用于在分切机处自动标记纸，纸板或纤维素卷筒纸的方法和装置，以便在后续整理步骤中识别辊。 这种整理操作包括例如辊运输，倒卷，片材或其它精加工步骤和辊包装。 卷标识码也用于与客户卷相关的物料管理。 发送离开分切机的辊组的辊识别信息，即从作为一组的分切机排出的辊的顺序被传送以用于辊标记设备，并且客户辊仅通过 滚筒打标设备和新卷防止以任何其他形式进入分切区域，除了新的卷组。 结果，每个卷组的正确识别数据连续可用于标记设备。

公开(公告)号：US06411186B1

公开(公告)日：2002-06-25

申请号：US09214801

申请日：1999-01-11

Applicant: Jorma Lilleberg ,  Esko Nieminen

Inventor： Jorma Lilleberg ,  Esko Nieminen

IPC: H04B7216

CPC classification number: H04B1/707

Abstract: A delay estimation method and a receiver in a radio system. Signals originate from one or several transmitters and propagate along several paths. One path (73-77) is selected at a time for estimation. The least squares minimization between the received signal and the code bank model is solved path by path (73-77) and delay by delay. The delay of only one selected path is changed at a time. Using the minimization results the delays of the other paths (73-77) remain unchanged. The minimization results establish the delay with the minimized result at most equal to the results for other delays. This delay is used as the constant value of the path (73-77) when the delays of the other paths are searched. The method provides the delays of all the paths (73-77) of all users simultaneously without information on user symbols or attenuation coefficients of the channel.

Abstract translation: 无线电系统中的延迟估计方法和接收机。 信号源自一个或多个发射机，并沿着几条路径传播。 一次选择一条路径（73-77）进行估计。 通过路径（73-77）和延迟延迟求解接收信号和码本模型之间的最小二乘法最小化。 一次只更改一个所选路径的延迟。 使用最小化结果，其他路径（73-77）的延迟保持不变。 最小化结果确定延迟，最小化结果最多等于其他延迟的结果。 当搜索其他路径的延迟时，该延迟被用作路径（73-77）的常数值。 该方法同时提供所有用户的所有路径（73-77）的延迟，而没有关于用户符号或信道的衰减系数的信息。

公开(公告)号：US08167117B2

公开(公告)日：2012-05-01

申请号：US12593200

申请日：2008-03-28

Applicant: Esko Nieminen ,  Markku Santala

Inventor： Esko Nieminen ,  Markku Santala

IPC: B65G25/00

CPC classification number: B65G1/08 ,  B65G47/266 ,  B65G2201/0232

Abstract: A sorting deck for paper, board, or pulp rolls has a plane (1) for transporting the rolls and controllable stops (2) for holding the rolls in place and releasing them. The stops (2) are positioned to form at least one line (3) in placed consecutively in the longitudinal direction (4) of the plane (1), and at least one row (5), in which the stops (2) are positioned adjacently to each other along the lateral direction (6) of the plane (1). At least some of the stops (2) are a collector (41) and a feeder (42), both of which can be moved freely between the hold and release positions, so that the travel of the rolls over the stop (2) can be optionally prevented, freely permitted, or permitted one roll at a time. The same sorting deck can be used to handle rolls of different widths.

Abstract translation: 用于纸张，纸板或纸浆辊的分拣板具有用于输送辊的平面（1）和用于将辊保持在适当位置并将其释放的可控制止挡（2）。 止动件（2）定位成形成在平面（1）的纵向方向上连续放置的至少一条线（3），以及至少一排（5），其中止动件（2） 沿着平面（1）的横向（6）彼此相邻地定位。 至少一些止动件（2）是收集器（41）和进料器（42），两者都可以在保持和释放位置之间自由移动，使得辊子在止动件（2）上的行进可以 一次可选地防止，自由允许或允许一卷。 相同的分拣台可用于处理不同宽度的卷。

公开(公告)号：US07839310B2

公开(公告)日：2010-11-23

申请号：US12378998

申请日：2009-02-19

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: H03M7/00

CPC classification number: H03M13/2993 ,  H03M13/2775 ,  H03M13/6525 ,  H03M13/653 ,  H03M13/6544 ,  H03M13/6558

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract translation: 为接收到的码字的系统比特生成第一组存储器空间地址; 为接收到的码字的第一组编码比特生成第二组存储器空间地址，其中第一组编码比特包括升序; 并且为接收的码字的第二组编码比特生成第三组存储器空间地址，其中第二组编码比特包括交织顺序。 通过使用第二组存储器空间中的地址访问第一组编码比特来并行地解码所接收码字的子码字。 接着，通过使用第三组存储器空间中的地址访问第二组编码比特来并行地解码所接收码字的另一子码字。 还详细说明了存储计算机程序的装置和存储器。

公开(公告)号：US08090896B2

公开(公告)日：2012-01-03

申请号：US12217333

申请日：2008-07-03

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: G06F12/00

CPC classification number: H04L49/901 ,  G06F9/345 ,  G06F9/3885 ,  G06F12/0607 ,  H03M13/276 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/6505 ,  H03M13/6566 ,  H04L47/14 ,  H04L49/90 ,  H04L49/9047 ,  Y02D10/13

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract translation: 存储体具有多个存储器。 在一个实施例中，前向单元以前向双向访问顺序将逻辑存储器地址应用于存储体，后向单元以向后双向访问顺序向存储体提供逻辑存储器地址，以及半蝶形网络（至少一半， 和8元组实施例中的桶形移位器）被布置在存储体和前向单元和后向单元之间。 生成一组控制信号，这些控制信号被施加到一半或更多个蝶形网络（以及当前的桶形移位器），以便在第一种情况下以线性顺序访问具有n元组并行性的存储体， 二次多项式次序，其中n = 2，4，8，16，32，...。 。 。 。 该访问用于逻辑地址的任何n元组，并且没有内存访问冲突。 以这种方式，存储器访问可以被控制数据解码。

公开(公告)号：US20100207789A1

公开(公告)日：2010-08-19

申请号：US12378998

申请日：2009-02-19

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: H03M7/00

CPC classification number: H03M13/2993 ,  H03M13/2775 ,  H03M13/6525 ,  H03M13/653 ,  H03M13/6544 ,  H03M13/6558

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract translation: 为接收到的码字的系统比特生成第一组存储器空间地址; 为接收到的码字的第一组编码比特生成第二组存储器空间地址，其中第一组编码比特包括升序; 并且为接收的码字的第二组编码比特生成第三组存储器空间地址，其中第二组编码比特包括交织顺序。 通过使用第二组存储器空间中的地址访问第一组编码比特来并行地解码所接收码字的子码字。 接着，通过使用第三组存储器空间中的地址访问第二组编码比特来并行地解码接收到的码字的另一子码字。 还详细说明了存储计算机程序的装置和存储器。

公开(公告)号：US20100005221A1

公开(公告)日：2010-01-07

申请号：US12217333

申请日：2008-07-03

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: G06F12/06

CPC classification number: H04L49/901 ,  G06F9/345 ,  G06F9/3885 ,  G06F12/0607 ,  H03M13/276 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/6505 ,  H03M13/6566 ,  H04L47/14 ,  H04L49/90 ,  H04L49/9047 ,  Y02D10/13

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract translation: 存储体具有多个存储器。 在一个实施例中，前向单元以前向双向访问顺序将逻辑存储器地址应用于存储体，后向单元以向后双向访问顺序向存储体提供逻辑存储器地址，以及半蝶形网络（至少一半， 和8元组实施例中的桶形移位器）被布置在存储体和前向单元和后向单元之间。 生成一组控制信号，这些控制信号被施加到一半或更多个蝶形网络（以及当前的桶形移位器），以便在第一种情况下以线性顺序访问具有n元组并行性的存储体， 二次多项式次序，其中n = 2，4，8，16，32，...。 。 。 。 该访问用于逻辑地址的任何n元组，并且没有内存访问冲突。 以这种方式，存储器访问可以被控制数据解码。

公开(公告)号：US07242723B2

公开(公告)日：2007-07-10

申请号：US10781492

申请日：2004-02-18

Applicant: Esko Nieminen

Inventor： Esko Nieminen

IPC: H04L23/02 ,  H03M13/03

CPC classification number: H04L1/006 ,  H03M13/23 ,  H03M13/4107 ,  H03M13/4161 ,  H03M13/6505 ,  H04L1/0054

Abstract: The invention relates to trellis code decoder. The decoder comprises a path metrics calculation unit for calculating path metrics over at least two trellis columns in a trellis, and a memory for storing path metrics of the trellis. The decoder further comprises an input multiplexer connected between the read interface of the memory and the input interface of the path metrics calculation unit, and an output multiplexer connected between the output interface of the path metrics calculation unit and the write interface of the memory. The decoder further comprises a control for controlling configuration of the input multiplexer and configuration of the output multiplexer on the basis of states of the trellis, which state of the trellis defines the way the old path metrics and the new path metrics relate to each other, whereby internal configuration of the path metrics calculation unit remains the same for different code constraint lengths.

Abstract translation: 本发明涉及网格码解码器。 解码器包括用于计算网格中的至少两个网格列的路径量度的路径度量计算单元，以及用于存储网格的路径度量的存储器。 解码器还包括连接在存储器的读接口和路径度量计算单元的输入接口之间的输入多路复用器，以及连接在路径度量计算单元的输出接口和存储器的写接口之间的输出多路复用器。 解码器还包括用于基于网格的状态来控制输入多路复用器的配置和输出多路复用器的配置的控制，网格的状态定义了旧路径度量和新路径量度相互关联的方式， 由此对于不同的码约束长度，路径度量计算单元的内部配置保持相同。