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    INDOOR NAVIGATION AND TRACKING WITH MESH NETWORK
    593.
    发明申请
    INDOOR NAVIGATION AND TRACKING WITH MESH NETWORK 有权

    公开(公告)号：US20210219097A1

    公开(公告)日：2021-07-15

    申请号：US16743854

    申请日：2020-01-15

    Applicant: STMicroelectronics International N.V.

    Inventor： Jitendra Jain ,  Alok Kumar Mittal

    IPC: H04W4/029 ,  H04W4/33

    Abstract: This application discloses systems, devices, and methods for indoor navigation and tracking with a mesh network. In one aspect, a navigation device includes a receiver configured to receive a locational signal from a node network. The locational signal identifies a respective node of the node network, and the node network is distributed throughout a physical space. The navigation device includes a memory storing a program and a processor in communication with the receiver and configured to execute the program to calculate a position of the navigation device from the identity of the respective node, determine a routing instruction from the position of the navigation device to a destination based on the position of the navigation device and a known mapping of the node network in the physical space, and update the position of the navigation device and the routing instruction as the navigation device moves through the physical space.

    MEMORY DEVICE AND METHOD OF OPERATING THEREOF
    594.
    发明申请
    MEMORY DEVICE AND METHOD OF OPERATING THEREOF 有权

    公开(公告)号：US20210193221A1

    公开(公告)日：2021-06-24

    申请号：US17129016

    申请日：2020-12-21

    Applicant: StMicroelectronics International N.V.

    Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Massimo Caruso ,  Cesare Torti

    IPC: G11C13/00

    Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.

    Methods and apparatus for data synchronization in systems having multiple clock and reset domains
    596.
    发明授权
    Methods and apparatus for data synchronization in systems having multiple clock and reset domains 有权

    公开(公告)号：US10999050B1

    公开(公告)日：2021-05-04

    申请号：US16865914

    申请日：2020-05-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Samiksha Agarwal

    IPC: H04L7/00

    Abstract: A data synchronization unit including first flip-flops, operating on a first clock domain and a reset of a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path configured to delay the request signal by a first delay and to generate an enable signal for recirculation multiplexers in accordance with the delayed request signal; a reset signal synchronization path configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of the recirculation multiplexers, a second input for receiving a reset value of a programmable register, the multiplexers being configured to selectively output signals at inputs to outputs.

    PROTECTION SCHEME FOR SENSOR SEGMENTATION IN VIRTUALIZATION APPLICATION
    599.
    发明申请
    PROTECTION SCHEME FOR SENSOR SEGMENTATION IN VIRTUALIZATION APPLICATION 有权

    公开(公告)号：US20210089651A1

    公开(公告)日：2021-03-25

    申请号：US16579415

    申请日：2019-09-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Deepak BARANWAL ,  Nirav Prashantkumar TRIVEDI ,  Sandip ATAL

    IPC: G06F21/55 ,  G06F21/75 ,  G06F9/455 ,  G06F13/16

    Abstract: An embedded system includes a peripheral and system-on-a-chip executing virtual machines and a hypervisor. The peripheral includes a crossbar circuit receiving digital sensor signals and selectively outputting the digital sensor signals to different outputs, queue circuits each receiving a different one of the digital sensor signals from the crossbar circuit, and queue protection circuits associated with the queue circuits and selectively permitting access to one of the queue circuits by the virtual machines. The hypervisor controls the queue protection circuits to set which of the virtual machines may access which queue circuits. A sensor protection circuit selectively permits reading of the digital sensor signals from the crossbar circuit by the queue circuits. The hypervisor controls the sensor protection circuit to set which of the queue circuits may access each of the digital sensor signals from the crossbar circuit.

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