公开(公告)号：US08836411B2

公开(公告)日：2014-09-16

申请号：US13726522

申请日：2012-12-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

IPC: G05F1/62 ,  H02M3/18 ,  G05F3/02 ,  H02M3/07 ,  H02M1/32

CPC classification number: G05F3/02 ,  H02M3/073 ,  H02M2001/322

Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

Abstract translation: 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。

公开(公告)号：US20140084367A1

公开(公告)日：2014-03-27

申请号：US13974936

申请日：2013-08-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Mandana Tadayoni ,  Yueh-Hsin Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66492 ,  H01L21/265 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833

Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

Abstract translation: 晶体管及其制造方法包括衬底，衬底上的导电栅极和导电栅极下的衬底中的沟道区。 第一和第二绝缘间隔件横向邻近导电栅极的第一和第二侧。 衬底中的源极区域与导电栅极和第一间隔物的第一侧相邻但是横向间隔开，并且衬底中的漏极区域与导电栅极的第二侧相邻但横向间隔开，并且第二 间隔 第一LD区域和第二LD区域分别位于衬底中并分别在沟道区域和源极或漏极区域之间横向延伸，每个区域的一部分没有设置在第一和第二间隔物之下，也不设置在导电栅极之下，并且每个具有掺杂剂浓度 比源区或漏区。

公开(公告)号：US08614924B2

公开(公告)日：2013-12-24

申请号：US13866966

申请日：2013-04-19

Applicant: Silicon Storage Technology Inc.

Inventor： Hieu Van Tran ,  Sakhawat M. Khan

IPC: G11C7/00

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract translation: 为数字多位非易失性存储器集成系统提供高速电压模式感测。 一个实施例具有本地源跟随器阶段，之后是高速公共源级。 另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。 另一个实施例具有公共源级，之后是源跟随器。 使用自动归零方案。 使用电容感测方案。 描述多级并行操作。