公开(公告)号：US20140185510A1

公开(公告)日：2014-07-03

申请号：US14199774

申请日：2014-03-06

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W52/02

CPC classification number: H04W52/0219 ,  H04W40/005 ,  H04W52/0216 ,  H04W52/0229 ,  H04W52/0258 ,  H04W72/1263 ,  H04W84/10 ,  H04W84/12 ,  Y02D70/142

Abstract: This invention relates to switching power saving modes and rescheduling communication frames for various periods of a beacon interval (BI) defined under WGA Draft Specification 0.8 for the personal basic service set (PBSS) and infrastructure BSS to achieve further power savings and other advantages. Stations can be awake during a contention-based period (CBP) if it is in active state and can schedule frames during a service period (SP) to allow the assigned receiver to transmit to the assigned initiator. Stations in a group can schedule a group address frame to be sent during the CBP and group SP of a specific periodic BI. Stations in peer-to-peer connection may directly notify its peer stations of its power saving mode and wakeup schedule. Stations of an infrastructure basic service set (BSS) can also use the same power saving mechanism as stations of a PBSS noting a difference where each BI will be an access point's (AP's) awake BI.

Abstract translation: 本发明涉及用于个人基本服务组（PBSS）和基础设施BSS的WGA草案规范0.8中定义的信标间隔（BI）的各个周期的切换省电模式和重新调度通信帧，以实现进一步的功率节省和其他优点。 如果处于活动状态，站可以在基于争用的周期（CBP）期间唤醒，并且可以在服务周期（SP）期间调度帧以允许所分配的接收者向所分配的发起者发送。 组中的站可以安排在特定周期性BI的CBP和组SP期间发送的组地址帧。 点对点连接的站点可以直接通知其对等站其省电模式和唤醒时间表。 基础设施基础服务集（BSS）的站也可以使用与PBSS站相同的省电机制，注意到每个BI将是接入点（AP）的清醒BI。

公开(公告)号：US08759874B1

公开(公告)日：2014-06-24

申请号：US13691070

申请日：2012-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

Abstract translation: 尽管FinFET和应变硅器件有所改进，晶体管在器件尺寸缩小的同时仍继续受到性能的降低。 这些特别包括在半导体沟道和衬底之间的电荷泄漏。 隔离沟道FinFET器件通过在沟道（鳍片）和衬底之间插入绝缘层来防止沟道对衬底的泄漏。 绝缘层物理和电气都将鳍片与衬底隔离开来。 为了形成隔离的FinFET器件，可以从硅表面，在提供相邻鳍片之间的局部绝缘的氮化物柱之间外延生长双层鳍片阵列。 然后，可以除去下部翅片层，同时留下上部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上翅片层下方的产生的间隙，以将翅片通道阵列与基底隔离。

公开(公告)号：US20140151746A1

公开(公告)日：2014-06-05

申请号：US13691070

申请日：2012-11-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

Abstract translation: 尽管FinFET和应变硅器件有所改进，晶体管在器件尺寸缩小的同时仍继续受到性能的降低。 这些特别包括在半导体沟道和衬底之间的电荷泄漏。 隔离沟道FinFET器件通过在沟道（鳍片）和衬底之间插入绝缘层来防止沟道对衬底的泄漏。 绝缘层物理和电气都将鳍片与衬底隔离开来。 为了形成隔离的FinFET器件，可以从硅表面，在提供相邻鳍片之间的局部绝缘的氮化物柱之间外延生长双层鳍片阵列。 然后，可以除去下部翅片层，同时留下上部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上翅片层下方的产生的间隙，以将翅片通道阵列与基底隔离。

公开(公告)号：US20140145666A1

公开(公告)日：2014-05-29

申请号：US14063163

申请日：2013-10-25

Applicant: STMicroelectronics, Inc.

Inventor： David F. Swanson

IPC: H02P7/00

CPC classification number: H02P7/00 ,  E05B77/12 ,  E05B81/06 ,  E05B81/54 ,  E05B81/62

Abstract: An integrated circuit is configured for controlling automobile door lock motors. The circuit includes half-bridge driver circuits, with each half-bridge driver circuit having an output node configured to be coupled to a door lock motor. A control circuit is configured to control driver operation of the half-bridge driver circuits. A current regulator circuit senses current sourced by or sunk by at least one of the half-bridge circuits. The control circuit responds to the current regulator circuit and the sensed current by controlling the driver operation to provide for a regulated current to be sourced by or sunk by said half-bridge circuit. The control circuit further controls the half-bridge driver circuits to enter a tri-state mode in order to support the making of BEMF measurements on the motor.

Abstract translation: 集成电路被配置用于控制汽车门锁电机。 电路包括半桥驱动器电路，每个半桥驱动器电路具有被配置为耦合到门锁电机的输出节点。 控制电路被配置为控制半桥驱动器电路的驱动器操作。 电流调节器电路感测由至少一个半桥电路供电或沉没的电流。 控制电路通过控制驱动器操作来响应电流调节器电路和感测电流，以提供由所述半桥电路供电或沉没的稳压电流。 控制电路进一步控制半桥驱动电路进入三态模式，以支持在电动机上进行BEMF测量。

公开(公告)号：US20140134808A1

公开(公告)日：2014-05-15

申请号：US14157947

申请日：2014-01-17

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Yiheng Xu ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract translation: 一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。 沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

公开(公告)号：US20140105131A1

公开(公告)日：2014-04-17

申请号：US14051583

申请日：2013-10-11

Applicant: STMICROELECTRONICS, INC.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W48/16

CPC classification number: H04W48/16 ,  H04W8/005 ,  H04W40/244 ,  H04W40/246 ,  H04W48/12

Abstract: A wireless network access point generates a fast initial link setup (FILS) discovery frame for broadcast to one or more wireless stations. The wireless network access point supports many operating channels including a primary channel. The FILS discovery frame includes a data field populated with an identification of a channel number for that primary channel of the wireless network access point. The FILS discovery frame includes another data field populated with a primary channel operating class identification. The broadcast FILS discovery frame further includes data indicating whether indicating whether multiple BSSIDs are supported. An FD capability field of the FILS discovery frame includes sub-fields indicating one or more of operation channel width, PHY type of the wireless access point, number of spatial streams supported by the wireless access point and multiple BSSIDs support provided by the wireless access point.

Abstract translation: 无线网络接入点生成用于广播到一个或多个无线站的快速初始链路建立（FILS）发现帧。 无线网络接入点支持许多操作信道，包括主信道。 FILS发现帧包括填充有无线网络接入点的主信道的信道号的标识的数据字段。 FILS发现帧包括填充有主信道操作类标识的另一数据字段。 广播FILS发现帧还包括指示是否指示是否支持多个BSSID的数据。 FILS发现帧的FD能力字段包括指示操作信道宽度，无线接入点的PHY类型，无线接入点支持的空闲数量的数量和由无线接入点提供的多个BSSID支持中的一个或多个的子字段 。

公开(公告)号：US20140092797A1

公开(公告)日：2014-04-03

申请号：US13631284

申请日：2012-09-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W52/02 ,  H04W56/00

CPC classification number: H04W52/0216 ,  Y02D70/122 ,  Y02D70/142

Abstract: Enhanced low power medium access (LPMA) processes involve the enhanced LPMA STA indicating low power capabilities during association and being allocated an AID. The AID(s) for one or a group of enhanced LPMA STA(s) are included in one TIM sent during a different BEACON interval than the AID(s) for another or another group of enhanced LPMA STA(s). In addition, or alternatively, the AID(s) for enhanced LPMA STA(s) are located at an edge of the AID set within a TIM, a portion of the TIM that may be easily truncated and therefore not sent. The enhanced LPMA STAs and associated access point negotiate unique offset and sleepinterval periods for polling or data uplink by the enhanced LPMA STAs.

Abstract translation: 增强的低功率介质访问（LPMA）处理涉及增强的LPMA STA，其指示关联期间的低功率能力并且被分配AID。 一个或一组增强型LPMA STA的AID包括在与另一组或另一组增强型LPMA STA的AID不同的BEACON间隔期间发送的一个TIM中。 另外或替代地，用于增强的LPMA STA的AID位于TIM内的AID集合的边缘，该TIM的一部分可以容易地被截断，因此不被发送。 增强的LPMA STA和相关联的接入点通过增强的LPMA STA协商轮询或数据上行链路的唯一偏移和休眠间隔周期。

公开(公告)号：US20140084465A1

公开(公告)日：2014-03-27

申请号：US13629402

申请日：2012-09-27

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract translation: 多个金属轨道形成在集成电路管芯内，堆叠在管芯内的三个金属层。 在中间金属层的金属轨道周围形成保护电介质层。 保护性介电层用作硬掩模，以在中间金属层之上和之下的金属层中限定金属轨道之间的接触通孔。

公开(公告)号：US20140084247A1

公开(公告)日：2014-03-27

申请号：US13931234

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L21/66

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract translation: 将金属量子点（例如，溴化银（AgBr）膜）引入MOSFET的源极和漏极区域可以通过调整阈值电压来帮助控制晶体管的性能。 如果溴化银膜富含溴原子，则沉积阴离子量子点，改变AgBr能隙以增加Vt，如果溴化银膜富含银原子，则沉积阳离子量子点，AgBr 能量间隙被改变以便降低Vt，不同尺寸的中性量子点的原子层沉积（ALD）也变化Vt。在膜沉积期间使用质谱仪可以帮助改变量子点膜的组成。 金属量子点可以结合到离子掺杂的源极和漏极区域中。 或者，金属量子点可以并入外延掺杂的源区和漏区。

公开(公告)号：US20140084245A1

公开(公告)日：2014-03-27

申请号：US13931096

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/127 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract translation: 金属量子点被并入到MOSFET阵列的掺杂源极和漏极区域中，以通过改变半导体晶体的能隙来帮助控制晶体管的性能。 在第一示例中，量子点被并入到离子掺杂的源极和漏极区域中。 在第二个例子中，量子点被并入外延掺杂的源区和漏区。