公开(公告)号：US10312090B2

公开(公告)日：2019-06-04

申请号：US16003058

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/311 ,  H01L21/033 ,  H01L27/108

Abstract: A patterning method is disclosed. A substrate having a hard mask layer and a first material layer formed thereon is provided. The first material layer is patterned into first array patterns and first peripheral patterns. The first array patterns are further transferred into first spacer patterns. Subsequently, a planarization layer and a second material layer are successively formed on the substrate. The second material layer is patterned into second array patterns and second peripheral patterns. The second array patterns are further transferred into second spacer patterns. The second spacer patterns partially overlap the first spacer patterns. The second peripheral patterns do not overlap the first peripheral pattern. The first spacer patterns not overlapped by the second spacer patterns are removed to obtain third array patterns. The hard mask layer is then etched using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask.

公开(公告)号：US10312080B2

公开(公告)日：2019-06-04

申请号：US15859750

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

公开(公告)号：US10304679B2

公开(公告)日：2019-05-28

申请号：US15876226

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Hsien-Shih Chu ,  Cheng-Yu Wang

IPC: H01L21/033 ,  H01L21/762

Abstract: A method of fabricating a mask includes providing a substrate. A first material layer is disposed on the substrate. Then, the first material layer is partly removed. A second trench is formed between the remaining first material layer. The second trench includes a height. Later, a second material layer is formed to conformally fill in the second trench. The second material layer includes a thickness. The thickness of the second material layer equals the height of the second trench. Finally, part of the second material layer is removed, and the remaining second material layer and the remaining first material layer comprise a second mask.

公开(公告)号：US20190157421A1

公开(公告)日：2019-05-23

申请号：US16258679

申请日：2019-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US10290728B2

公开(公告)日：2019-05-14

申请号：US15487817

申请日：2017-04-14

Applicant: United Microelectronics Corp.

Inventor： Chu-Ming Ma ,  Chun-Yi Lin ,  Hung-Chi Huang ,  Hsien-Ta Chung

IPC: H01L29/36 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first doped region, a second doped region, a first dielectric layer, a third doped region, a fourth doped region, a second dielectric layer and a conductive layer. The substrate has a first trench in a first area and a second trench in a second area. The first and second doped regions are disposed in the substrate respectively at two side of the first trench. The first dielectric layer is disposed on the sidewall of the first trench. The third doped region is disposed around the second trench. The fourth doped region is disposed in the third doped region at one side of the second trench. The second dielectric layer is disposed on the sidewall and bottom of the second trench. The conductive layer is disposed in the first and second trenches.

公开(公告)号：US10290641B1

公开(公告)日：2019-05-14

申请号：US15871920

申请日：2018-01-15

Applicant: United Microelectronics Corp.

Inventor： Wan-Xun He ,  Su Xing

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12

Abstract: A semiconductor device has a 6T SRAM cell formed on a substrate. The SRAM cell includes a first and a second PMOS transistors formed over an N-well line in a substrate. A first and a second NMOS transistors are formed over a first P-well line in the substrate at a first side of the N-well line. A third and a fourth NMOS transistors are formed over a second P-well line in the substrate at a second side of the N-well line. A first gate line connects gates of the first PMOS transistor and the first NMOS transistor. A second gate line connects a gate of the second NMOS transistor. A third gate line connects gates of the second PMOS transistor and the third NMOS transistor. A fourth gate line connects a gate of the fourth NMOS transistor. The first gate line and the third gate line are in L-shape.

公开(公告)号：US10283564B1

公开(公告)日：2019-05-07

申请号：US15807528

申请日：2017-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chao-Ching Hsieh ,  Yu-Ru Yang ,  Hsiao-Pang Chou

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/02 ,  H01L29/08 ,  H01L21/265

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

公开(公告)号：US10283415B2

公开(公告)日：2019-05-07

申请号：US16132460

申请日：2018-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US20190123135A1

公开(公告)日：2019-04-25

申请号：US16129782

申请日：2018-09-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L49/02 ,  H01L27/108

Abstract: The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer.

公开(公告)号：US20190123104A1

公开(公告)日：2019-04-25

申请号：US15818673

申请日：2017-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Hsiao-Pang Chou

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.