公开(公告)号：US20060053189A1

公开(公告)日：2006-03-09

申请号：US11161674

申请日：2005-08-11

Applicant: Michael Mantor

Inventor： Michael Mantor

IPC: G06F7/38

CPC classification number: G06T15/005 ,  G06F11/2028 ,  G06F11/2038 ,  G06F11/2048

Abstract: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.

Abstract translation: 简而言之，图形数据处理逻辑包括多个并行算术逻辑单元（ALU），诸如浮点处理器或任何其它合适的逻辑，其在像素数据和顶点数据（或两者）中的至少一个上作为向量处理器，以及 可编程存储元件，其包含表示多个算术逻辑单元中的哪一个不接收用于处理的数据的数据。 图形数据处理逻辑还包括并行ALU数据打包逻辑，其可操作地耦合到多个算术逻辑处理单元和可编程存储元件，以仅对由可编程存储元件中的数据标识的多个算术逻辑单元打包数据 被启用。

公开(公告)号：US20060053188A1

公开(公告)日：2006-03-09

申请号：US11161672

申请日：2005-08-11

Applicant: Michael Mantor ,  Ralph Taylor ,  Robert Hartog

Inventor： Michael Mantor ,  Ralph Taylor ,  Robert Hartog

IPC: G06F7/38

CPC classification number: G06F11/2028 ,  G06F11/2038 ,  G06F11/2048

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract translation: 具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。 输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。 当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。 冗余的并行ALU然后对有缺陷的ALU进行操作。 输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于 由其他电路进一步处理。

公开(公告)号：US06999098B2

公开(公告)日：2006-02-14

申请号：US10459790

申请日：2003-06-12

Applicant: Mark M. Leather

Inventor： Mark M. Leather

IPC: G09G5/02

CPC classification number: G09G5/363 ,  G09G2320/0276

Abstract: Graphics processing circuitry includes processing circuitry operative to generate pixel information in response to primitive information, and a correction circuit, coupled to the processing circuitry, operative to generate gamma corrected pixel information in response to the pixel information. The correction circuit converts the floating point pixel information generated by the processing circuitry into a gamma corrected fixed-point value so that gamma space pixel data is stored in the frame buffer. This fixed point gamma corrected pixel information, converted from the floating point pixel information, compensates for the non-linear display characteristics exhibited by current display devices. This results in the display output being more accurate; thereby, improving the appearance quality of the resulting image.

Abstract translation: 图形处理电路包括可操作以响应于原始信息生成像素信息的处理电路，以及耦合到处理电路的校正电路，可操作以响应于像素信息产生伽马校正的像素信息。 校正电路将由处理电路产生的浮点像素信息转换为伽马校正定点值，使得伽马空间像素数据存储在帧缓冲器中。 从浮点像素信息转换出的该固定点伽马校正像素信息补偿当前显示装置所呈现的非线性显示特性。 这导致显示输出更准确; 从而改善所得图像的外观质量。

公开(公告)号：US20050289377A1

公开(公告)日：2005-12-29

申请号：US10878466

申请日：2004-06-28

Applicant: Tien D. Luong ,  Erwin Pang

Inventor： Tien D. Luong ,  Erwin Pang

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3203 ,  Y02D10/126

Abstract: Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.

Abstract translation: 简而言之，本发明包括用于降低图形处理装置中的功耗的方法和装置。 该装置和方法包括可操作以从存储器模块接收存储器模块状态信号的存储器模块监视装置。 存储器模块监视装置用于响应于存储器模块状态信号而产生时钟控制信号。 该装置和方法还包括耦合到监视模块的时钟周期降低电路。 时钟周期降低电路接收时钟控制信号。 时钟周期降低电路响应于时钟控制信号产生减小的周期时钟信号，使得减小的周期时钟信号降低图形处理装置中的功耗。

公开(公告)号：US06970173B2

公开(公告)日：2005-11-29

申请号：US09954685

申请日：2001-09-14

Applicant: Alec A. Ciolac

Inventor： Alec A. Ciolac

IPC: G09G5/14 ,  G09G5/39 ,  G09G5/395 ,  G06F12/02

CPC classification number: G09G5/14 ,  G09G5/39 ,  G09G5/395 ,  G09G2340/12

Abstract: A system and method is provided for supporting a multiple display configuration through a single connected display device. The present disclosure allows a system desktop to be expanded across multiple virtual displays without a need for extra hardware to support multiple display devices. A display driver partitions a frame buffer of a video card into portions. Each portion is used to support a different virtual display. The display driver reports a number of virtual displays to an operating system and provides pointers to addresses associated with the portions of the frame buffer. The operating system treats each frame buffer portion as a separate frame buffer and stores video data for each virtual display in an associated frame buffer portion. The display driver selects a virtual display from a set of multiple virtual displays and routes video data from the frame buffer portion associated with the selected display for output on a connected display device.

Abstract translation: 提供了一种用于通过单个连接的显示设备支持多显示器配置的系统和方法。 本公开允许在多个虚拟显示器之间扩展系统桌面，而不需要额外的硬件来支持多个显示设备。 显示驱动程序将视频卡的帧缓冲器分成多个部分。 每个部分用于支持不同的虚拟显示。 显示驱动程序向操作系统报告多个虚拟显示，并提供指向与帧缓冲器的部分相关联的地址的指针。 操作系统将每个帧缓冲器部分视为单独的帧缓冲器，并将每个虚拟显示器的视频数据存储在相关联的帧缓冲器部分中。 显示驱动器从一组多个虚拟显示器中选择虚拟显示器，并且从与所选显示器相关联的帧缓冲器部分路由视频数据，以在连接的显示设备上输出。

公开(公告)号：US20050251826A1

公开(公告)日：2005-11-10

申请号：US10839062

申请日：2004-05-05

Applicant: Stephen Orr

Inventor： Stephen Orr

IPC: G06F3/00 ,  G06F13/00 ,  H04N7/16 ,  H04N5/445

CPC classification number: H04N21/4524 ,  H04N5/44543 ,  H04N7/163 ,  H04N21/4532 ,  H04N21/454 ,  H04N21/482

Abstract: A method apparatus for automated display video programming guide information includes filtering programming information using filtering rules to determine viewing events of interest to a user. The method and apparatus further includes displaying on a first screen portion, the viewing events in a chronological order based on a display time for each of the viewing events. The method and apparatus further includes displaying a selector in the first screen portion such that the selector is operative to select one of the viewing events and displaying on a second screen portion, event information relating to a selected one of the plurality viewing events when the selector is proximate to one of the viewing events. The method and apparatus further includes resolving a scheduling conflict between a first viewing event and second viewing event to generate a list of program guide information.

Abstract translation: 用于自动显示视频节目指南信息的方法装置包括使用过滤规则过滤节目信息，以确定用户感兴趣的观看事件。 该方法和装置还包括基于每个观看事件的显示时间，在第一屏幕部分上以时间顺序显示观看事件。 所述方法和装置还包括在第一屏幕部分中显示选择器，使得选择器可操作以选择观看事件之一并在第二屏幕部分上显示与选择器相关的多个观看事件中的所选择的一个的事件信息 接近其中一个观看事件。 所述方法和装置还包括解决第一观看事件和第二观看事件之间的调度冲突以产生节目指南信息的列表。

公开(公告)号：US20050243203A1

公开(公告)日：2005-11-03

申请号：US10837991

申请日：2004-05-03

Applicant: Philip Swan

Inventor： Philip Swan

IPC: H04N5/44 ,  H04N7/01 ,  H04N7/26 ,  H04N11/20

CPC classification number: H04N7/0137 ,  H04N7/012 ,  H04N19/112

Abstract: An apparatus and method for image rendering includes a first buffer operative to receive first video data. A motion mad updater receives video data from the first buffer and updates a motion map using the first video data. A grain information generator is coupled to the first buffer and receives the first video data to generate slope information based on the first video data. A grain information filter receives the slope information and filters the slope information to generate filtered slope information. A spatially interpolated field generator receives the filtered slope information and generates a spatially interpolated field. A maximum difference value generator generates a maximum difference value based on the update motion map. A base value generator receives the first video data and the spatially interpolated field and generates a base value therefrom. A missing video data generator generates missing first video data.

Abstract translation: 一种用于图像渲染的装置和方法包括可操作以接收第一视频数据的第一缓冲器。 运动疯狂更新器从第一缓冲器接收视频数据，并使用第一视频数据更新运动图。 谷物信息发生器耦合到第一缓冲器并且接收第一视频数据以基于第一视频数据生成斜率信息。 谷物信息滤波器接收斜率信息并对斜率信息进行滤波以产生滤波斜率信息。 空间内插场产生器接收经滤波的斜率信​​息并产生空间内插场。 最大差值发生器基于更新运动图生成最大差值。 基值生成器接收第一视频数据和空间内插字段，并从其生成基值。 丢失的视频数据生成器生成缺少的第一个视频数据。

公开(公告)号：US20050225376A1

公开(公告)日：2005-10-13

申请号：US10820556

申请日：2004-04-08

Applicant: Oscar Kin Law

Inventor： Oscar Kin Law

IPC: H03K3/01 ,  H03K19/00

CPC classification number: H03K19/0013 ,  H03K19/0016

Abstract: An adaptive supply voltage and body bias apparatus includes a master controller including an operation state value. The apparatus and method includes a dynamic voltage supplier coupled to the master controller operative to receive a supply voltage indicator. The apparatus and method includes an adaptive body biaser coupled to the master controller operative to receive a body bias indicator. Furthermore, the apparatus and method includes a plurality of computing devices each having one of a plurality of threshold voltages. The plurality of computing devices are operative to receive the supply voltage from the dynamic voltage supplier and a bias voltage from the adaptive body biaser for optimized power supply in conjunction with reduction of power leakage in view of the varying threshold voltage of the computing devices.

Abstract translation: 自适应电源电压和体偏置装置包括具有操作状态值的主控制器。 该装置和方法包括耦合到主控制器的动态电压供应器，其操作以接收电源电压指示器。 该装置和方法包括耦合到主控制器的自适应主体偏置器，其操作以接收体偏置指示器。 此外，该装置和方法包括各自具有多个阈值电压之一的多个计算装置。 考虑到计算装置的变化的阈值电压，多个计算装置可操作以从动态电压供应器接收供电电压和来自自适应主体偏置器的偏置电压，用于优化的电力供应以及减少功率泄漏。

公开(公告)号：US06950105B2

公开(公告)日：2005-09-27

申请号：US10161022

申请日：2002-06-03

Applicant: Vladimir Giemborek ,  Syed Hussain ,  David Chih

Inventor： Vladimir Giemborek ,  Syed Hussain ,  David Chih

IPC: G06F1/26 ,  G06F1/32 ,  G06F15/16 ,  G06T1/00 ,  G06T1/60 ,  G09G5/36

CPC classification number: G06F1/3215 ,  G06F1/324 ,  G06F1/325 ,  Y02D10/126

Abstract: A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requirements. Power is conserved by reducing clock speeds from unnecessarily high rates to a rate that can satisfy current display mode settings and other graphics processing demands.

Abstract translation: 方法和装置匹配在图形加速器中使用或由图形加速器使用的一个或多个时钟速度，以便将图形处理要求与时钟源或源的速度相匹配。 在软件控制下调整时钟速度以匹配当前要求。 通过将时钟速度从不必要的高速率降低到可以满足当前显示模式设置和其他图形处理需求的速率来节省功率。

公开(公告)号：US20050198468A1

公开(公告)日：2005-09-08

申请号：US10768804

申请日：2004-01-30

Applicant: Norman Rubin ,  Richard Bagley

Inventor： Norman Rubin ,  Richard Bagley

IPC: G06F15/00

CPC classification number: G06F8/443

Abstract: A method and apparatus for superword register value numbering includes hashing an operation code and the value numbers of a plurality of sources to generate a first hash value. The method and apparatus further includes retrieving an operation value number from the first hash table based on the first hash value. The method and apparatus further includes generating a result value number based on a previous bit hash value and the operation value number. The result value number is a combination of the operation value numbers for each component having a live indicator and a previous value numbers for the components without the live indicator. Thereupon, the method and apparatus includes searching a second hash table using the result value number. As such, the method and apparatus provides using two separate hash tables for value numbering with superword instructions.

Abstract translation: 用于超字数据寄存器值编号的方法和装置包括对操作码和多个源的值编号进行散列以产生第一散列值。 该方法和装置还包括基于第一散列值从第一散列表中检索操作值号。 所述方法和装置还包括基于先前的比特哈希值和所述操作值号来生成结果值号。 结果值编号是具有实时指示器的每个组件的操作值编号与没有实时指示器的组件的先前值编号的组合。 因此，该方法和装置包括使用结果值号搜索第二散列表。 因此，该方法和装置提供使用两个单独的散列表来进行带有超字指令的值编号。