公开(公告)号：US08593470B2

公开(公告)日：2013-11-26

申请号：US10906559

申请日：2005-02-24

申请人： John Bruno ,  Erwin Pang

发明人： John Bruno ,  Erwin Pang

IPC分类号： G06F13/372

CPC分类号： G06F13/1689 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G09G5/363 ,  G09G5/39 ,  G09G2300/0473 ,  Y02D10/126 ,  Y02D10/14

摘要： A power adjustment circuit includes memory controller logic that is couplable to system memory or other memory if desired. The memory control logic is operative to provide a variable memory clock signal to the system memory and to place the system memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal. Thereafter, the memory clock control logic adjusts the frequency of the memory clock signal to a lower (or higher) frequency clock signal, and in response to the frequency of the memory clock signal becoming stable, the memory clock control logic restores the memory to a normal mode using the lower adjusted frequency memory clock signal. As such, a dynamic memory clock switching mechanism is employed for quickly varying the frequency of memory modules for discrete graphics processors, graphics processors integrated on a chip, or any other processors such that the memory clock can be reduced to a lower frequency in real time to save power.

摘要翻译： 功率调节电路包括如果需要可连接到系统存储器或其它存储器的存储器控​​制器逻辑。 存储器控制逻辑可操作以向系统存储器提供可变存储器时钟信号，并将系统存储器置于自刷新模式，其中自刷新模式不需要存储器时钟信号。 此后，存储器时钟控制逻辑将存储器时钟信号的频率调整到较低（或更高）的频率时钟信号，并且响应于存储器时钟信号的频率变得稳定，存储器时钟控制逻辑将存储器恢复到 正常模式使用较低的调整频率存储时钟信号。 因此，动态存储器时钟切换机制用于快速改变用于独立图形处理器，集成在芯片上的图形处理器或任何其它处理器的存储器模块的频率，使得存储器时钟可以实时地降低到更低的频率 节省电力。

公开(公告)号：US07467318B2

公开(公告)日：2008-12-16

申请号：US10675525

申请日：2003-09-29

申请人： John Bruno ,  Oleksandr Khodorkovsky ,  Erwin Pang ,  Gia Phan

发明人： John Bruno ,  Oleksandr Khodorkovsky ,  Erwin Pang ,  Gia Phan

IPC分类号： G06F1/04

CPC分类号： G06F1/206

摘要： An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

摘要翻译： 一种适应性温度相关时钟反馈控制系统和方法，用于将时钟信号的频率自适应地改变到电路，使得所述电路可以基于电路结温在最大安全工作时钟频率下工作。 时钟控制系统包括热传感器和与温度相关的动态超频发生器电路。 热传感器检测对应于半导体管芯上的电路的至少一部分的结温。 温度相关的动态超频发生器电路基于半导体管芯结温度改变时钟信号，使得时钟信号在与检测到的结温相关联的最高可能工作频率下工作。 如果结温度低于较低的结温阈值，则时钟信号的频率从第一频率增加到至少第二频率和第三频率。

公开(公告)号：US20060187226A1

公开(公告)日：2006-08-24

申请号：US10906559

申请日：2005-02-24

申请人： John Bruno ,  Erwin Pang

发明人： John Bruno ,  Erwin Pang

IPC分类号： G06F13/372

CPC分类号： G06F13/1689 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G09G5/363 ,  G09G5/39 ,  G09G2300/0473 ,  Y02D10/126 ,  Y02D10/14

摘要： A power adjustment circuit includes memory controller logic that is couplable to system memory or other memory if desired. The memory control logic is operative to provide a variable memory clock signal to the system memory and to place the system memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal. Thereafter, the memory clock control logic adjusts the frequency of the memory clock signal to a lower (or higher) frequency clock signal, and in response to the frequency of the memory clock signal becoming stable, the memory clock control logic restores the memory to a normal mode using the lower adjusted frequency memory clock signal. As such, a dynamic memory clock switching mechanism is employed for quickly varying the frequency of memory modules for discrete graphics processors, graphics processors integrated on a chip, or any other processors such that the memory clock can be reduced to a lower frequency in real time to save power.

摘要翻译： 功率调节电路包括如果需要可连接到系统存储器或其它存储器的存储器控​​制器逻辑。 存储器控制逻辑可操作以向系统存储器提供可变存储器时钟信号，并将系统存储器置于自刷新模式，其中自刷新模式不需要存储器时钟信号。 此后，存储器时钟控制逻辑将存储器时钟信号的频率调整到较低（或更高）的频率时钟信号，并且响应于存储器时钟信号的频率变得稳定，存储器时钟控制逻辑将存储器恢复到 正常模式使用较低的调整频率存储时钟信号。 因此，动态存储器时钟切换机制用于快速改变用于独立图形处理器，集成在芯片上的图形处理器或任何其它处理器的存储器模块的频率，使得存储器时钟可以实时地降低到更低的频率 节省电力。

公开(公告)号：US20100194361A1

公开(公告)日：2010-08-05

申请号：US12366233

申请日：2009-02-05

申请人： Peter Thomas Hardman ,  Erwin Pang ,  Sanjiv K. Lakhanpal

发明人： Peter Thomas Hardman ,  Erwin Pang ,  Sanjiv K. Lakhanpal

IPC分类号： G05F1/00

CPC分类号： H02M3/1584 ,  H02M3/1588 ,  H02M2003/1586 ,  Y02B70/1466

摘要： Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

摘要翻译： 用于在开关模式转换器电路中执行DC至DC功率转换的技术包括动态开关切换，相位脱落，对称相位电路拓扑和非对称相位电路拓扑的组合。 在本发明的至少一个实施例中，一种操作功率转换器电路的方法包括当功率转换器电路被配置为第一操作模式时，使用第一数量的开关器件操作第一相位开关电路部分。 第一个数字大于零。 该方法包括当功率转换器电路被配置为第二操作模式时，使用第一数量的开关器件来操作第一相位开关电路部分。 该方法包括当功率转换器电路被配置为第二操作模式时，使用第二数量的开关装置来操作第二相位开关电路部分。 第二个数字大于第一个数字。

公开(公告)号：US20050071705A1

公开(公告)日：2005-03-31

申请号：US10675525

申请日：2003-09-29

申请人： John Bruno ,  Oleksandr Khodorkovsky ,  Erwin Pang ,  Gia Phan

发明人： John Bruno ,  Oleksandr Khodorkovsky ,  Erwin Pang ,  Gia Phan

IPC分类号： G06F1/20 ,  G06F1/04

CPC分类号： G06F1/206

摘要： An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

摘要翻译： 一种适应性温度相关时钟反馈控制系统和方法，用于将时钟信号的频率自适应地改变到电路，使得所述电路可以基于电路结温在最大安全工作时钟频率下工作。 时钟控制系统包括热传感器和与温度相关的动态超频发生器电路。 热传感器检测对应于半导体管芯上的电路的至少一部分的结温。 温度相关的动态超频发生器电路基于半导体管芯结温度改变时钟信号，使得时钟信号在与检测到的结温相关联的最高可能工作频率下工作。 如果结温度低于较低的结温阈值，则时钟信号的频率从第一频率增加到至少第二频率和第三频率。

公开(公告)号：US06847335B1

公开(公告)日：2005-01-25

申请号：US09181973

申请日：1998-10-29

申请人： Chen-Jen Jerry Chang ,  Erwin Pang ,  David Chih

发明人： Chen-Jen Jerry Chang ,  Erwin Pang ,  David Chih

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  G09G2370/047

摘要： A circuit and method serves as a slave interface to support both register read/write and monitor detection operations by a graphics controller chip, or other display data source, with a plurality of display devices. The circuit supports differing monitor detection protocols including, for example, I2C protocol and non-DDC type protocols. The circuit may be set in two modes, a register mode and a bypass mode. The register mode is used to facilitate standard I2C protocol to a display device. Display detection bypass circuitry is used to selectively bypass the register based display detector interface by connecting input pins to any two of a plurality of I/O pins so that the system may be used for monitor detection of a plurality of different display devices, such as CRTs and LCDs to facilitate multiprotocol display detection.

摘要翻译： 电路和方法用作从接口，以支持具有多个显示设备的图形控制器芯片或其他显示器数据源的寄存器读/写和监视器检测操作。 该电路支持不同的监视器检测协议，包括例如I 2 C协议和非DDC类型协议。 电路可以设置为寄存器模式和旁路模式两种模式。 寄存器模式用于促进显示设备的标准I 2 C协议。 显示检测旁路电路用于通过将输入引脚连接到多个I / O引脚中的任何两个来选择性地旁路基于寄存器的显示检测器接口，使得系统可以用于多个不同显示设备的监视器检测，诸如 CRT和LCD，以便于多协议显示检测。

公开(公告)号：US07948222B2

公开(公告)日：2011-05-24

申请号：US12366233

申请日：2009-02-05

申请人： Peter Thomas Hardman ,  Erwin Pang ,  Sanjiv K. Lakhanpal

发明人： Peter Thomas Hardman ,  Erwin Pang ,  Sanjiv K. Lakhanpal

IPC分类号： G05F1/00

CPC分类号： H02M3/1584 ,  H02M3/1588 ,  H02M2003/1586 ,  Y02B70/1466

摘要： Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

摘要翻译： 用于在开关模式转换器电路中执行DC至DC功率转换的技术包括动态开关切换，相位脱落，对称相位电路拓扑和非对称相位电路拓扑的组合。 在本发明的至少一个实施例中，一种操作功率转换器电路的方法包括当功率转换器电路被配置为第一操作模式时，使用第一数量的开关器件操作第一相位开关电路部分。 第一个数字大于零。 该方法包括当功率转换器电路被配置为第二操作模式时，使用第一数量的开关器件来操作第一相位开关电路部分。 该方法包括当功率转换器电路被配置为第二操作模式时，使用第二数量的开关装置来操作第二相位开关电路部分。 第二个数字大于第一个数字。

公开(公告)号：US07500123B2

公开(公告)日：2009-03-03

申请号：US10878466

申请日：2004-06-28

申请人： Tien D. Luong ,  Erwin Pang

发明人： Tien D. Luong ,  Erwin Pang

IPC分类号： G06F1/26

CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

摘要： Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.

摘要翻译： 简而言之，本发明包括用于降低图形处理装置中的功耗的方法和装置。 该装置和方法包括可操作以从存储器模块接收存储器模块状态信号的存储器模块监视装置。 存储器模块监视装置用于响应于存储器模块状态信号而产生时钟控制信号。 该装置和方法还包括耦合到监视模块的时钟周期降低电路。 时钟周期降低电路接收时钟控制信号。 时钟周期降低电路响应于时钟控制信号产生减小的周期时钟信号，使得减小的周期时钟信号降低图形处理装置中的功耗。

公开(公告)号：US20050289377A1

公开(公告)日：2005-12-29

申请号：US10878466

申请日：2004-06-28

申请人： Tien D. Luong ,  Erwin Pang

发明人： Tien D. Luong ,  Erwin Pang

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

摘要： Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.

摘要翻译： 简而言之，本发明包括用于降低图形处理装置中的功耗的方法和装置。 该装置和方法包括可操作以从存储器模块接收存储器模块状态信号的存储器模块监视装置。 存储器模块监视装置用于响应于存储器模块状态信号而产生时钟控制信号。 该装置和方法还包括耦合到监视模块的时钟周期降低电路。 时钟周期降低电路接收时钟控制信号。 时钟周期降低电路响应于时钟控制信号产生减小的周期时钟信号，使得减小的周期时钟信号降低图形处理装置中的功耗。

公开(公告)号：US06535217B1

公开(公告)日：2003-03-18

申请号：US09233815

申请日：1999-01-20

申请人： David Chih ,  Erwin Pang

发明人： David Chih ,  Erwin Pang

IPC分类号： G06F1314

CPC分类号： G09G5/006 ,  G09G5/366

摘要： An integrated circuit for graphics processing that includes a configurable display interface includes video graphics circuitry, a data encoder, transmission circuitry and configuration registers. The video graphics circuitry produces video data that is formatted to drive a display. The data encoder is operably coupled to the video graphics circuitry and encodes the digital video data to produce transmission data. The transmission data is then provided to the transmission circuitry operably coupled to the data encoder. The transmission circuitry combines the transmission data with control information that is retrieved from registers included in the integrated circuit. The transmission circuitry transmits the transmission data over a plurality of differential signals, where the swing amplitude of the differential signals is configured using additional registers included in the integrated circuit.

摘要翻译： 包括可配置显示接口的用于图形处理的集成电路包括视频图形电路，数据编码器，传输电路和配置寄存器。 视频图形电路产生格式化为驱动显示器的视频数据。 数据编码器可操作地耦合到视频图形电路并对数字视频数据进行编码以产生传输数据。 然后将传输数据提供给可操作地耦合到数据编码器的传输电路。 传输电路将传输数据与从包含在集成电路中的寄存器检索的控制信息进行组合。 传输电路通过多个差分信号传输传输数据，其中使用包括在集成电路中的附加寄存器来配置差分信号的摆幅。