公开(公告)号：US4271522A

公开(公告)日：1981-06-02

申请号：US42299

申请日：1979-05-25

申请人： M. Jacques Droux ,  Claude R. Cardot

发明人： M. Jacques Droux ,  Claude R. Cardot

IPC分类号： G11B20/18 ,  G11B21/10 ,  G06F11/30

CPC分类号： G11B20/18

摘要： Errors in reading data with a magnetic head from reference zones on trackst differing radii of a magnetic memory disc rotating at constant angular velocity are determined. Each track includes at least one reference zone including a plurality of initial cells. Each initial cell has magnetic flux variations which when read by the head result in a first waveform that includes undulations enabling the head to be properly servo controlled to a position over the center of the track and a further undulation that is distinguishable from the head positioning undulations because it has a larger amplitude. The initial cells are followed by plural binary bit representing data cells each having magnetic flux variations which when read by the head result in a second waveform including a data representing undulation that has approximately the same amplitude as the further undulations. The undulations are susceptible of having varying amplitudes as the head is positioned at different positions of the disc. In response to a detected peak amplitude of each further undulation of one reference zone a threshold is set for the further undulations of subsequently read first waveforms and for the address cells of the reference zone. An error in a cell is signalled if the set threshold is exceeded by the amplitude of undulations of the first and second waveforms at incorrect times.

摘要翻译： 确定在以恒定角速度旋转的磁记录盘的不同半径处的轨道上的来自参​​考区域的磁头读取数据的错误。 每个轨道包括至少一个包括多个初始单元的参考区域。 每个初始单元都具有磁通量变化，当磁头读数导致第一波形包括波动时，可以将磁头适当地伺服控制到轨道中心的位置，而另外的起伏可以与磁头定位波动区分开 因为它具有较大的振幅。 初始单元之后是多个二进制位，表示数据单元，每个数据单元各自具有磁通量变化，当磁头读取时，导致第二个波形，包括表示具有与其他波动大致相同幅度的波形的数据。 当头部位于盘的不同位置时，波动可能具有变化的幅度。 响应于一个参考区域的每个进一步波动的检测峰值幅度，为随后读取的第一波形和参考区域的地址单元的进一步起伏设置阈值。 如果在不正确的时间超过第一和第二波形的起伏幅度超过设定的阈值，则发出信号中的错误信号。

公开(公告)号：US4271480A

公开(公告)日：1981-06-02

申请号：US896189

申请日：1978-04-14

申请人： Daniel Vinot

发明人： Daniel Vinot

IPC分类号： H04L13/08 ,  G06F5/06 ,  G06F5/10 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F5/10

摘要： An apparatus for transferring data blocks of variable lengths between intaces of different widths. The apparatus includes a series memory of the first-in, first-out type (FIFO) and an interface means at the input and output of the series memory. The interface means has a first means for storage of input data words and a second means for storage of output data words, the two storage means being of different storage capacity. Means are included for signalling to external devices when the first storage means and the series memory are empty and ready to receive data. Means are also included for controlling in response to an external signal the width of the output data words.

摘要翻译： 用于在不同宽度的接口之间传送可变长度的数据块的装置。 该装置包括先进先出类型（FIFO）的串行存储器和串行存储器的输入和输出端的接口装置。 接口装置具有用于存储输入数据字的第一装置和用于存储输出数据字的第二装置，所述两个存储装置具有不同的存储容量。 当第一存储装置和串行存储器为空且准备好接收数据时，包括用于向外部装置发信号的装置。 还包括用于响应于外部信号来控制输出数据字的宽度的装置。

公开(公告)号：US4266286A

公开(公告)日：1981-05-05

申请号：US92562

申请日：1979-11-08

申请人： Andre Richard

发明人： Andre Richard

IPC分类号： G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4094

摘要： A memory of the MOS N channel type comprising two half-memories each conting the same number of columns, each column being bisected at the center by a refreshing amplifier. A bus is alotted to each half-memory and is connectable to any half-column in the half-memory which is addressed so as to read and rewrite in the refreshing phase. The extracting and rewriting arrangement incorporates a flip-flop having its inputs connected to the buses by a differential circuit and its outputs connected to inputs of a read and rewrite circuit. The buses are initialized at a low potential and a reference potential is applied to one bus when the other bus is connected to a half-column. Transient interference rise on the selected bus above the disturbance threshold of the refreshing amplifier is prevented.

摘要翻译： MOS N沟道型的存储器包括两个半存储器，每个半存储器包含相同数量的列，每列通过刷新放大器在中心被二等分。 总线分配给每个半存储器，并且可连接到半存储器中的任何半字节，这些半存储器被寻址以在刷新阶段读取和重写。 提取和重写装置包括其输入端通过差分电路连接到总线的触发器，其输出连接到读取和重写电路的输入。 当另一个总线连接到半柱时，总线被初始化为低电位，并且将参考电位施加到一个总线。 所选择的总线上的瞬态干扰上升高于刷新放大器的干扰阈值。

公开(公告)号：US4258400A

公开(公告)日：1981-03-24

申请号：US34747

申请日：1979-04-30

申请人： Jean-Pierre Lazzari

发明人： Jean-Pierre Lazzari

IPC分类号： G11B21/21 ,  G11B5/60 ,  G11B21/20 ,  G11B17/32

CPC分类号： G11B5/60 ,  G11B21/20

摘要： A platform for supporting at least one magnetic transducer for reading from and/or recording on a data carrier. The platform is supported from a carrier arm adapted to position the platform over the data carrier which may be a multi-track disc. The magnetic transducer is supported in the lower face of the main body of the platform. The lower face includes a plurality of skids and one or more grooves which receive a rigid strut for suspending the platform over the carrier. The strut is secured in the groove(s) with the plane of the strut passing through the center of gravity of the platform. The strut may be secured to a frame surrounding the platform which in turn may be secured to a further concentric frame also surrounding the platform. The strut includes a constriction located at the virtual axis of rotation or axis of oscillation of the platform and at which point the cross-sectional area of the strut is at a minimum. The axis of symmetry of the constriction lies in a direction perpendicular to the major dimension of the strut and coincides with the virtual axis of rotation or axis of oscillation such that the sum of the bending moment of the constriction and the moment of the pressure forces exerted on the lower face of the main body is zero.

摘要翻译： 用于支持用于从数据载体上读取和/或记录的至少一个磁换能器的平台。 平台由适于将平台定位在可以是多轨盘的数据载体上的承载臂支撑。 磁换能器支撑在平台主体的下表面。 下表面包括多个滑板和一个或多个凹槽，其接收用于将平台悬挂在载体上的刚性支柱。 支柱固定在槽中，支柱的平面穿过平台的重心。 支柱可以固定到围绕平台的框架，该框架又可以固定到也围绕平台的另一同心框架。 支柱包括位于虚拟的旋转轴线或平台的振动轴线处的收缩部，并且在该点处支柱的横截面积最小。 收缩的对称轴位于垂直于支柱的主尺寸的方向上，与假想的旋转轴线或振动轴线重合，使得收缩部的弯曲力矩与施加的压力的力矩之和 在主体的下面是零。

公开(公告)号：US4223392A

公开(公告)日：1980-09-16

申请号：US873845

申请日：1978-01-31

申请人： Francis Lemaire ,  Pierre Salkazanov ,  Robert Bavoux

发明人： Francis Lemaire ,  Pierre Salkazanov ,  Robert Bavoux

IPC分类号： G06F1/10 ,  G06M3/02 ,  G06F1/04 ,  H03K3/00

CPC分类号： G06F1/10

摘要： A plurality of sub-clock signals are derived from a main clock signal sou by advancing a shift register and a counter with pulses from the main clock source. The shift register is selectively loaded with a desired combination of sub-clock bits in response to a predetermined number of main clock pulses being supplied to the counter. The sub-clock signals are derived from output terminals at different stages of the shift register. The state of the sub-clock signals can be selectively frozen by decoupling pulses from the main clock source to inputs of the counter and shift register.

摘要翻译： 通过使来自主时钟源的脉冲推移移位寄存器和计数器，从主时钟信号源导出多个子时钟信号。 响应于提供给计数器的预定数量的主时钟脉冲，移位寄存器选择性地加载期望的子时钟位组合。 子时钟信号从移位寄存器的不同级的输出端子导出。 子时钟信号的状态可以通过从主时钟源去除脉冲到计数器和移位寄存器的输入来选择性地冻结。

公开(公告)号：US4185190A

公开(公告)日：1980-01-22

申请号：US876139

申请日：1978-02-08

申请人： Gilles J. M. Bottard ,  Michel Henry

发明人： Gilles J. M. Bottard ,  Michel Henry

IPC分类号： G06F11/277 ,  G06F17/40 ,  H03M7/30 ,  G06F11/00

CPC分类号： H03M7/30 ,  G06F11/277

摘要： Apparatus is disclosed for cumulative summing and compressing data items each of which is comprised of b binary elements. The summing and compressing apparatus is associated with control means to process each data item in a cumulative summing and compression cycle, and is comprised of an input buffer register which is designated to store a data item to be processed at the beginning of each cycle, a set of n intermediate registers occupying serial positions 1 ot n each of which has b storage locations, an adder circuit, an output buffer register made up of n sections having b storage locations, and transfer circuits which are connected to the control means, which produces a succession of control signals for successively interconnecting (1) the registers in serial positions 1 to (n-1) and the input buffer register, to the adder circuit in order to add the contents of the (n-1) registers and the data item to be processed at the beginning of each cycle and to transfer the result of this addition to the input buffer register; (2) the registers in serial positions 2 to n, to the registers in serial positions 1 to (n-1)in order to transfer the content of each of the registers in serial positions 2 to n to the register which precedes it in the order given, (3) the register in serial position n and the input buffer register, to the adder circuit in order to add the contents of these registers and to transfer the result of this addition to the register in serial position n, and (4) the registers in serial positions 1 to n, in parallel to respective ones of the n sections of the output bufrer register in order to transfer the contents of the n registers to the output buffer register so that, at the end of an N.sup.th cumulative summing and compression cycle, the contents of the output buffer register is a data item which has been compressed from a set of N data items which have been processed by the apparatus in N accumulation and compression cycles.The invention is particularly concerned with locating a failure occurring in a data processing unit by determining a symptom which is the result of accumulation and packing a series of partial symptoms.

公开(公告)号：US4172277A

公开(公告)日：1979-10-23

申请号：US875538

申请日：1978-02-06

申请人： Denis Pinson

发明人： Denis Pinson

IPC分类号： H02M3/335 ,  H02M7/00 ,  H02P13/00

CPC分类号： H02M3/33546

摘要： A system for controlling chopping for a converter in a DC electrical power supply.A transistor is arranged for chopping the DC input voltage which is connected to a chopping transformer. A control transistor controls the chopping transistor by means of pulses which it receives from a clock, via a pulse transformer.

摘要翻译： 一种用于控制直流电源中的转换器的斩波的系统。

公开(公告)号：US4656474A

公开(公告)日：1987-04-07

申请号：US799300

申请日：1985-11-20

申请人： Jean H. Mollier ,  Charles J. Saada

发明人： Jean H. Mollier ,  Charles J. Saada

IPC分类号： B42D15/10 ,  G07F7/10 ,  G09C1/00 ,  H04L9/32 ,  H04Q9/00 ,  G06K5/00

CPC分类号： G06Q20/40975 ,  G06Q20/341 ,  G06Q20/3674 ,  G07F7/1008 ,  H04L9/3247

摘要： A process and a device for authenticating the signature of a signed message includes a nominal signature card (1a) coupled to a transmitting device 1 which sends signed messages. The card (1a) includes at least one memory (5) in which there are secretly prerecorded at least one secret key (S) and one program (P) which automatically processes the signature of a message (M), as well as circuits (6) for computing the signature (SG). A control card (3b), which is not nominal, is coupled to a device (3) for receiving signed messages. The card (3b) includes at least one memory in which there are secretly prerecorded at least the secret key (S) and the program (P) for recomputing via processing circuits (15) the signature (SG) of the received message (M).

摘要翻译： 用于认证签名消息的签名的过程和设备包括耦合到发送签名消息的发送设备1的标称签名卡（1a）。 卡（1a）包括至少一个存储器（5），其中秘密预先记录了至少一个秘密密钥（S）和一个程序（P），其自动处理消息（M）的签名以及电路（ 6）用于计算签名（SG）。 不标称的控制卡（3b）被耦合到用于接收签名消息的设备（3）。 卡（3b）包括至少一个存储器，其中秘密地预先记录了秘密密钥（S）和程序（P），用于经由处理电路（15）重新计算接收到的消息（M）的签名（SG） 。

公开(公告)号：US4611869A

公开(公告)日：1986-09-16

申请号：US326818

申请日：1981-12-02

申请人： Jean Bonnefoy

发明人： Jean Bonnefoy

IPC分类号： H01R4/30 ,  H01L23/32 ,  H01R4/46 ,  H01R11/01 ,  H01R12/50 ,  H01R12/71 ,  H01R13/621 ,  H05K1/18 ,  H05K3/32

CPC分类号： H01L23/32 ,  H01R12/714 ,  H05K3/325 ,  H01L2924/0002 ,  H01R4/46

摘要： The invention relates to apparatus for clamping superimposed conductive elements (11, 13) disposed in aligned groups by means of a clip device (22, 23) such that an integrated circuit device may be removably connected to a printed circuit card with a predetermined force being applied uniformly across all the superimposed elements. In accordance with the invention, at least one of the clips (22, 23), in the free state, has a cambered form, equivalent to the elastic deformation of an initially straight beam of uniform section and of the same length mounted on two simple supports spaced this length and uniformly charged over this length.The invention is primarily used for the electrical interconnection of integrated circuit devices to printed circuit cards.

摘要翻译： 本发明涉及通过夹子装置（22,23）夹紧设置成对齐的组的叠加的导电元件（11,13）的设备，使得集成电路器件可以以预定的力可拆卸地连接到印刷电路板 均匀地施加在所有叠加的元件上。 根据本发明，处于自由状态的夹子（22,23）中的至少一个具有弧形形状，相当于安装在两个简单的部件上的相同长度的初始直的梁的弹性变形 支撑间隔该长度并在该长度上均匀充电。 本发明主要用于集成电路器件与印刷电路卡的电互连。

公开(公告)号：US4538321A

公开(公告)日：1985-09-03

申请号：US505980

申请日：1983-06-20

申请人： Jean-Jacques Binder ,  Bernard Cherbuy

发明人： Jean-Jacques Binder ,  Bernard Cherbuy

IPC分类号： G03G15/08 ,  G03G15/00 ,  G03G15/095 ,  G03G19/00 ,  G03G21/10

CPC分类号： G03G19/00 ,  G03G15/095

摘要： The invention relates to a device that permits removal of excess developer particles on the surface of a recording element and comprises a suction conduit (22) having at one end a port (23) in the form of a slot and at its other end a cylindrical chamber (25) which communicates with said conduit. The generators of the chamber run parallel to the port (23). The chamber includes a suction port (32) which is connected to a suction source, and an air inlet port (31) which discharges into the free atmosphere (31).

摘要翻译： 本发明涉及一种允许在记录元件的表面上去除过量的显影剂颗粒的装置，并且包括一个抽吸管道（22），该抽吸管道的一端具有一个狭槽形式的端口（23），而在另一端具有圆柱形 室（25），其与所述导管连通。 室的发生器平行于端口（23）延伸。 所述室包括连接到吸入源的吸入口（32）和排出到自由气氛（31）中的空气入口（31）。