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公开(公告)号：US20160103781A1
公开(公告)日：2016-04-14
申请号：US14600016
申请日：2015-01-20
申请人： ALI Corporation
发明人： Kuo-Kai Lin , Wei-Chun Kao , Ching-Chung Cheng
CPC分类号： G06F13/4282 , G06F13/4072 , H04B17/00 , H04B2001/6912
摘要： An envelope detection device for detecting a transmission signal of a high speed serial communication includes: an operation circuit, for receiving the transmission signal and generating a set of operated outputs according to the transmission signal and at least one reference signal; a reference signal generating circuit coupled to the operation circuit, for providing the reference signal to the operation circuit, wherein the reference signal generating circuit is operable to provide the reference signal with different voltage levels; and a comparing circuit coupled to the operation circuit, for comparing the set of calculated outputs to generate a comparison result. The envelope detection device detects a transmission state and a disconnect state of the high speed serial communication according to the comparison result generated based on the reference signals at different voltage levels.
摘要翻译： 用于检测高速串行通信的发送信号的包络检测装置包括：运算电路，用于接收发送信号，并根据发送信号和至少一个参考信号产生一组操作的输出; 参考信号发生电路，耦合到所述操作电路，用于将所述参考信号提供给所述操作电路，其中所述参考信号发生电路可操作以向所述参考信号提供不同的电压电平; 以及耦合到所述操作电路的比较电路，用于比较所述一组计算的输出以产生比较结果。 包络检测装置根据基于不同电压电平的基准信号生成的比较结果来检测高速串行通信的发送状态和断开状态。
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公开(公告)号：US20160092327A1
公开(公告)日：2016-03-31
申请号：US14563317
申请日：2014-12-08
申请人： ALi Corporation
发明人： Yu-Feng Kang , Qian-Zhi Wang
CPC分类号： G06F11/26 , G06F11/2242 , G06F11/36 , G06F11/362
摘要： The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores.
摘要翻译： 本发明涉及多核处理器的调试系统和调试方法。 调试系统包括调试主机，目标处理器和映射协议转换设备。 调试主机包括调试器，目标处理器包括多个核心。 映射和协议转换设备连接在调试主机和目标处理器之间，识别每个核心所属的核心架构，并将每个核心分别映射到根据核心的至少一个进程的至少一个线程 每个核心所属的架构。 之后，调试器根据进程对目标处理器执行调试过程，线程对应于每个内核。
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63.发明授权Baseline wander compensating method, baseline calibration module and ethernet transceiver using the same 有权基线漂移补偿方法，基线校准模块和以太网收发器使用相同公开(公告)号：US09294383B2
公开(公告)日：2016-03-22
申请号：US14306282
申请日：2014-06-17
申请人： ALI CORPORATION
IPC分类号： H04L12/26
摘要： The present disclosure illustrates a baseline wander compensating method adapted for compensating baseline wander induced in an Ethernet transceiver. The baseline wander compensating method comprises following steps. Firstly, an output packet is detected. Next, a detection result of the output packet and a predetermined value are compared, and a control signal is generated correspondingly. Based on the control signal, a first calibration signal or a second calibration signal is selected, and a calibrating calculation is executed for the selected one of the first calibration signal and a second calibration signal. Next, an input signal is compensated according to a baseline calibration value generated from the calibrating calculation.
摘要翻译： 本公开示出了适用于补偿以太网收发器中引起的基线漂移的基线漂移补偿方法。 基线漂移补偿方法包括以下步骤。 首先，检测出输出包。 接下来，比较输出分组的检测结果和预定值，并且相应地生成控制信号。 基于控制信号，选择第一校准信号或第二校准信号，并且对所选择的第一校准信号和第二校准信号执行校准计算。 接下来，根据从校准计算产生的基线校准值来补偿输入信号。
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公开(公告)号：US09185322B2
公开(公告)日：2015-11-10
申请号：US14255434
申请日：2014-04-17
申请人： ALi Corporation
发明人： Hou-Kuan Sung , Chih-Yu Chuang , Yue-Yong Chen
摘要： A digital video broadcast receiver including a frequency synthesizer, a plurality of frequency dividing-phase shifting circuits, an antenna and a plurality of signal processing modules is provided. The frequency synthesizer synthesizes a first frequency signal. The frequency dividing-phase shifting circuits individually perform a frequency dividing-phase shifting operation on the first frequency signal to generate a plurality of first signals having different frequencies and a plurality of second signals corresponding to the first signals, where each of the first signals is orthogonal to the corresponding second signal. The antenna receives a radio frequency signal. The signal processing modules respectively obtain a plurality of signal components belonging to different sub-bands from the radio frequency signal according to the first signals and the second signals.
摘要翻译： 提供了包括频率合成器，多个分频移相电路，天线和多个信号处理模块的数字视频广播接收机。 频率合成器合成第一频率信号。 分频移相电路分别对第一频率信号执行分频移相操作，以产生具有不同频率的多个第一信号和对应于第一信号的多个第二信号，其中每个第一信号为 与相应的第二信号正交。 天线接收射频信号。 信号处理模块根据第一信号和第二信号分别从射频信号获得属于不同子带的多个信号分量。
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公开(公告)号：US20240331353A1
公开(公告)日：2024-10-03
申请号：US18492751
申请日：2023-10-23
申请人： ALi Corporation
发明人： Lun Liang
IPC分类号： G06V10/764 , G06V10/75
CPC分类号： G06V10/764 , G06V10/751
摘要： Disclosed are an image processing method and an image processing apparatus. An original image including a plurality of pixels is obtained. The plurality of pixels include a first pixel. N target pixel coordinates are recorded. The N target pixel coordinates form M target coordinate sets. M and N are integers greater than 0. The first pixel is associated with a first target coordinate set among the M target coordinate sets by utilizing a first classification method according to an original pixel coordinate of the first pixel. The first pixel is mapped to one of the N target pixel coordinates in the first target coordinate set by utilizing a second classification method. The original pixel coordinate of the first pixel is replaced with one of the N target pixel coordinates to convert the original image into an adjusted image.
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公开(公告)号：US20240321828A1
公开(公告)日：2024-09-26
申请号：US18500076
申请日：2023-11-01
申请人： ALi Corporation
发明人： Liang-Cai Zeng , YUN-JU HSIEH
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L25/0657 , H01L24/48 , H01L25/0655 , H01L2224/4814 , H01L2224/48149 , H01L2224/48229 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/14361
摘要： An integrated circuit structure and a chip are provided. The chip includes a first pad set, a second pad set, a connection circuit, and a signal pad set. The first pad set includes a plurality of first pads. The second pad set includes a plurality of second pads respectively corresponding in position to the first pads. Each of the first pads and the corresponding second pad are electrically coupled to each other through the connection circuit so as to be operable by choosing one therefrom. The signal pad set arranged between the first pad set and the second pad set and includes a plurality of signal pads.
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公开(公告)号：US11747844B2
公开(公告)日：2023-09-05
申请号：US17518589
申请日：2021-11-04
申请人： ALi Corporation
发明人： Chih-Yuan Hsu , Chien-Yuan Lu
IPC分类号： G05F1/46
摘要： A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.
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公开(公告)号：US20220147080A1
公开(公告)日：2022-05-12
申请号：US17518589
申请日：2021-11-04
申请人： ALi Corporation
发明人： Chih-Yuan Hsu , Chien-Yuan Lu
IPC分类号： G05F1/46
摘要： A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.
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公开(公告)号：US20220141436A1
公开(公告)日：2022-05-05
申请号：US17488340
申请日：2021-09-29
申请人： ALi Corporation
发明人： Lun Liang , Zhao-Dong Zhang
摘要： A projection device and a projection image correction method are provided. Four target coordinates of four target vertices forming a target quadrilateral boundary are obtained. A first trapezoidal boundary is obtained according to a predetermined image boundary and a first coordinate component of each of the four target coordinates. At least one edge of the target quadrilateral boundary is extended until intersecting with at least one of two reference line segments to obtain a second trapezoidal boundary. Bases of the first trapezoidal boundary are perpendicular to bases of the second trapezoidal boundary. First direction scaling processing is performed according to the first trapezoidal boundary, and second direction scaling processing is performed according to the second trapezoidal boundary, to scale an original image into a target image block aligned with the target quadrilateral boundary in an output image. The projection device projects the output image to display a rectangular projection image.
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公开(公告)号：US20210083657A1
公开(公告)日：2021-03-18
申请号：US17011917
申请日：2020-09-03
申请人： ALi Corporation
发明人： Chih-Yuan Hsu
摘要： A control circuit for controlling signal rising time and falling time is provided. The circuit includes multiple data flip-flops, multiple controllable delay circuits, and multiple current source circuits. The data flip-flops are triggered by clock signals to output a plurality of data signals. The controllable delay circuits delay the data signals, based on corresponding delay amounts, to generate a plurality of activation signals. Each of the current source circuits determines whether to output a unit current to a signal output terminal according to a level of one of the activation signals. Rising or falling time for an output signal of the signal output terminal to rise or fall to a predetermined level is determined according to a cycle time length of the clock signal and the delay amount of each of the controllable delay circuits.
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