公开(公告)号：US20090310416A1

公开(公告)日：2009-12-17

申请号：US12547102

申请日：2009-08-25

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.

摘要翻译： 用于提供选择性压实验证和/或选择性压缩的非易失性存储器件，以利于利用NAND架构在存储器件中紧固阈值电压分布。 通过在NAND串的不到所有字线上提供压缩验证和/或压缩，可以通过在NAND串的所有字线上同时执行的现有方法来实现分配的增加的紧缩。

公开(公告)号：US07616489B2

公开(公告)日：2009-11-10

申请号：US11349854

申请日：2006-02-08

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/115

摘要： The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of memory cells, arranged in row and column fashion, is formed on each second well region. Corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.

摘要翻译： 本发明提供了方法和装置。 存储器阵列具有第一导电类型的第一阱区。 在第一阱区中形成有第二导电类型的多个第二阱区。 第二阱区彼此电隔离。 在每个第二阱区域上形成以行和列方式布置的多个存储单元。 相应的第二阱区的存储单元的相应行通常耦合到字线。

公开(公告)号：US07580286B2

公开(公告)日：2009-08-25

申请号：US12042021

申请日：2008-03-04

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.

摘要翻译： 用于提供选择性压实验证和/或选择性压缩的非易失性存储器件，以利于利用NAND架构在存储器件中紧固阈值电压分布。 通过在NAND串的不到所有字线上提供压缩验证和/或压缩，可以通过在NAND串的所有字线上同时执行的现有方法来实现分配的增加的紧缩。

公开(公告)号：US07551510B2

公开(公告)日：2009-06-23

申请号：US11635708

申请日：2006-12-07

申请人： Jin-Man Han ,  Aaron Yip

发明人： Jin-Man Han ,  Aaron Yip

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/76 ,  G11C29/82 ,  Y02D10/13

摘要： A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

摘要翻译： 非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。 包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。 这些字线驱动器具有全局字线的一部分作为输入。 期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。 这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。

公开(公告)号：US07486530B2

公开(公告)日：2009-02-03

申请号：US11116842

申请日：2005-04-28

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

IPC分类号： G11C15/00 ,  G11C7/06 ,  G11C16/04

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

摘要翻译： 描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较 数据位并产生指示数据匹配或不匹配的信号标志。 这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。 在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或 结果逻辑组合以指示完整数据块的匹配或不匹配。

公开(公告)号：US07400549B2

公开(公告)日：2008-07-15

申请号：US11116597

申请日：2005-04-28

申请人： Jin-Man Han ,  Aaron Yip

发明人： Jin-Man Han ,  Aaron Yip

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/76 ,  G11C29/82 ,  Y02D10/13

摘要： A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

摘要翻译： 非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。 包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。 这些字线驱动器具有全局字线的一部分作为输入。 期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。 这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。

公开(公告)号：US20070300012A1

公开(公告)日：2007-12-27

申请号：US11474436

申请日：2006-06-26

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G06F13/00

CPC分类号： G06F12/0811

摘要： A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.

摘要翻译： 一种能够顺利地输出多页缓存数据同时减轻通常由取样和传送操作引起的任何中断的存储器件。 存储器件从第一页输出缓存的数据，而来自第二页的数据被提取到读出放大器电路中。 当第一页的输出到达预定的传送点时，来自第二页的获取的数据的一部分在被缓存的第一页的其余部分被输出的同时被传送到高速缓存。 在第二页的第一部分的输出以很少或没有中断的情况下开始输出来自第一页的所有数据之后，第二页的其余部分被传送到高速缓存。

公开(公告)号：US20070285988A1

公开(公告)日：2007-12-13

申请号：US11842531

申请日：2007-08-21

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/12 ,  G11C7/06

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US07254049B2

公开(公告)日：2007-08-07

申请号：US11580660

申请日：2006-10-13

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

IPC分类号： G11C15/00 ,  G11C7/10

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

公开(公告)号：US20070047311A1

公开(公告)日：2007-03-01

申请号：US11216742

申请日：2005-08-31

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.

摘要翻译： 用于提供选择性压实验证和/或选择性压缩的非易失性存储器件，以利于利用NAND架构在存储器件中紧固阈值电压分布。 通过在NAND串的不到所有字线上提供压缩验证和/或压缩，可以通过在NAND串的所有字线上同时执行的现有方法来实现分配的增加的紧缩。