公开(公告)号：US20100029933A1

公开(公告)日：2010-02-04

申请号：US12514356

申请日：2006-12-26

Applicant: Nitin Sopanrao Patil ,  Syed Idris Hussaini ,  Ashish Kumar Singh ,  Rakesh Bhaiyyaram Mendhe

Inventor： Nitin Sopanrao Patil ,  Syed Idris Hussaini ,  Ashish Kumar Singh ,  Rakesh Bhaiyyaram Mendhe

IPC: C07D498/16 ,  C12P17/18

CPC classification number: C07D498/18

Abstract: The present invention relates to a pure form of rapamycin with a total impurity content less than 1.2%; a process for recovery and purification of rapamycin comprising steps of (a) treating the fermentation broth, extracts or solutions containing rapamycin with water immiscible solvent and concentration; (b) addition of a water miscible solvent to effect separation of impurities present; (c) optionally, binding of the solvent containing the product from step (b) to an inert solid, washing the solid with a base and acid, followed by elution; (d) subjecting the elute from step (c) or the solvent containing the product from step (b) to silica gel chromatography; (e) crystallization of the product obtained from step (d); (f) subjecting a solution of the product from step (e) to hydrophobic interaction or reversed phase chromatography; and (g) re-crystallization to afford rapamycin in substantially pure form.

Abstract translation: 本发明涉及总杂质含量小于1.2％的纯形式的雷帕霉素; 一种回收和纯化雷帕霉素的方法，包括以下步骤：（a）用与水不混溶的溶剂和浓度处理含有雷帕霉素的发酵液，提取物或溶液; （b）加入水混溶性溶剂以分离存在的杂质; （c）任选地，将含有步骤（b）的产物的溶剂与惰性固体结合，用碱和酸洗涤固体，随后洗脱; （d）使来自步骤（c）的洗脱液或含有步骤（b）的产物的溶剂经硅胶色谱法; （e）从步骤（d）获得的产物的结晶; （f）使来自步骤（e）的产物的溶液进行疏水相互作用或反相色谱; 和（g）重结晶以提供基本上纯的形式的雷帕霉素。

公开(公告)号：US20090310516A1

公开(公告)日：2009-12-17

申请号：US12477751

申请日：2009-06-03

Applicant: Sandesh Goel ,  Ashish Kumar Shukla

Inventor： Sandesh Goel ,  Ashish Kumar Shukla

IPC: H04H20/71 ,  H04W74/00

CPC classification number: H04W74/0808 ,  H04L12/1886 ,  H04L12/189 ,  H04L45/16 ,  H04L47/12 ,  H04W28/0294 ,  H04W40/24 ,  H04W74/02

Abstract: A frame groupcast system for a mesh node in a mesh network having a plurality of mesh nodes includes a transceiver that receives a groupcast frame and a groupcast determination module that determines whether to forward the received groupcast frame based on at least one measurement.

Abstract translation: 在具有多个网格节点的网状网络中的网状节点的帧群播放系统包括接收群播帧的收发信机和基于至少一次测量来确定是否转发所接收的群播帧的群播广播确定模块。

公开(公告)号：US20080070631A1

公开(公告)日：2008-03-20

申请号：US11901191

申请日：2007-09-15

Applicant: Ashish Kumar

Inventor： Ashish Kumar

IPC: H04M1/00

CPC classification number: H04M1/72547 ,  G06F21/88 ,  H04M1/66 ,  H04M1/72563 ,  H04W8/08 ,  H04W8/16 ,  H04W12/12 ,  H04W60/00

Abstract: Provided is a method for tracking any mobile electronic device which accesses wireless or wired network using Instant Messaging (IM). The mobile device, capable of instant messenger (IM) functionality, allows storage of one or more IM IDs in a separate non-volatile memory. When the mobile device is lost/stolen, and another person changes the SIM card, the phone verifies if the SIM card is the same as that of the owner by matching the IMSI numbers of the two. If there is a mismatch, the mobile device triggers the tracking feature. The tracking feature automatically and stealthily transmits instant messages to the stored messenger IDs. Furthermore, with video/voice capability in the IM client, there is a provision for transmitting live video/voice of the person using the mobile phone after the tracking feature is enabled as video calls or voice calls respectively.

Abstract translation: 提供了一种用于跟踪使用即时消息（IM）访问无线或有线网络的任何移动电子设备的方法。 支持即时通讯（IM）功能的移动设备允许将一个或多个IM ID存储在单独的非易失性存储器中。 当移动设备丢失/被盗时，另一人改变SIM卡时，手机通过匹配两者的IMSI号来验证SIM卡是否与所有者相同。 如果不匹配，移动设备会触发跟踪功能。 跟踪功能自动并隐藏地将即时消息传送到存储的信使ID。 此外，在IM客户端中具有视频/语音功能，在跟踪功能分别作为视频呼叫或语音呼叫启用之后，存在用于使用移动电话发送人的实时视频/语音的规定。

公开(公告)号：US07271616B2

公开(公告)日：2007-09-18

申请号：US11190509

申请日：2005-07-26

Applicant: Ashish Kumar Goel ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Davinder Aggarwal

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K19/17764 ,  H03K19/17736

Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.

Abstract translation: 用于减小现场可编程门阵列（FPGA）中的回读时间的改进的数字电路包括具有多个锁存器的移位寄存器和提供给锁存器的时钟和复位信号。 在移位寄存器的每对锁存器之间提供互连电路，用于从期望的锁存器或锁存器提供选择性数据帧。 将控制信号发生器连接到所述互连电路的控制输入端可以快速回读所选择的数据帧，从而减少调试FPGA所花费的时间。

公开(公告)号：US07206919B2

公开(公告)日：2007-04-17

申请号：US10319436

申请日：2002-12-13

Applicant: Ashish Kumar Goel ,  Manish Agarwal

Inventor： Ashish Kumar Goel ,  Manish Agarwal

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F17/5054

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit defines partial configuration requirements, and contains at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. The configuration loading unit provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements without providing commands corresponding to any addresses outside of said configuration requirements.

Abstract translation: 一种用于实现可重构设备的快速部分配置的系统和方法包括配置定义单元和配置加载单元。 配置定义单元定义部分配置要求，并且至少包含用于部分重配置的配置数据的起始地址，指定要重新配置的连续位置的数量的数据大小以及对应于相邻位置的期望配置数据。 配置加载单元提供根据部分配置要求将配置数据加载到可重新配置设备中，而不提供与所述配置要求之外的任何地址相对应的命令。

公开(公告)号：US20060152965A1

公开(公告)日：2006-07-13

申请号：US11323953

申请日：2005-12-30

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G11C11/00

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an input terminal of one of the access transistors so that the access transistors coupled to the outputs from one of the memory cells share one of the wordlines and are coupled to different bitlines. A wordline driver is coupled to each wordline with the ability of generating a variable voltage at its output responsive to the wordline driver control inputs and voltage at its ground supply node. A plurality of grouped voltage supply lines are coupled to a group of the wordline drivers for inducing a variable reference voltage or ground supply at the ground supply node. A voltage switching logic switches the voltage for the variable ground supply responsive to a ground control input.

Abstract translation: 存储器包括多个存取晶体管，其中每个存取晶体管在其控制端耦合到一条字线，并在其输出端连接到一条位线。 多个存储单元具有耦合到一个存取晶体管的输入端的每个输出，使得耦合到来自存储单元之一的输出的存取晶体共享一条字线，并耦合到不同的位线。 字线驱动器耦合到每个字线，其能够响应于字线驱动器控制输入和其接地电源节点处的电压而在其输出处产生可变电压。 多个组合的电压供应线耦合到一组字线驱动器，用于在接地电源节点处引入可变参考电压或地电源。 电压开关逻辑根据接地控制输入切换可变接地电源的电压。

公开(公告)号：US07035132B2

公开(公告)日：2006-04-25

申请号：US10426004

申请日：2003-04-29

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G11C11/00

CPC classification number: G11C7/18 ,  G11C8/14

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

Abstract translation: 一种改进的多字线存储器架构，其提供减少的位线耦合以增加速度并降低功耗，包括用于将相邻位单元连接到不同字线的交错布置，耦合到用于共享相邻位单元的位线的复用布置。

公开(公告)号：US06894541B2

公开(公告)日：2005-05-17

申请号：US10684076

申请日：2003-10-10

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G01R15/00 ,  G11C7/02 ,  G11C7/06 ,  H03F3/45

CPC classification number: G11C7/065 ,  G11C7/02

Abstract: A sense amplifier includes a feedback controlled bit line access scheme that feeds a sense amplifier output signal back to control operation of its associated bit line access transistor. This feedback may be implemented using a pair of inverter circuits each coupling a respective output signal to the control gate of the associated access transistor. Alternatively, the feedback may be implement using a logic gate which logically combines the sense amplifier output signals together to generate an output signal for controlling operation of both access transistors. The logic gate is preferably a NAND gate. The sense amplifier further includes a cross-connected feedback inversion circuit which inverts a sense amplifier output signal from a first latch inverter for application to a conducting line of a second latch inverter.

Abstract translation: 读出放大器包括反馈控制的位线访问方案，其将读出放大器输出信号反馈到其相关联的位线存取晶体管的操作。 该反馈可以使用一对逆变器电路来实现，每个逆变器电路将相应的输出信号耦合到相关联的存取晶体管的控制栅极。 或者，可以使用将读出放大器输出信号逻辑地组合在一起以产生用于控制两个存取晶体管的操作的输出信号的逻辑门来实现反馈。 逻辑门优选地是NAND门。 读出放大器还包括一个交叉连接的反馈反相电路，它将来自第一锁存逆变器的读出放大器输出信号反相，以应用于第二锁存逆变器的导线。

公开(公告)号：US20240338679A1

公开(公告)日：2024-10-10

申请号：US18626026

申请日：2024-04-03

Applicant: Ashish Kumar

Inventor： Ashish Kumar

IPC: G06Q20/36 ,  H04L9/00

CPC classification number: G06Q20/367 ,  H04L9/50

Abstract: A method and system for creating and managing secure tokens associated with users and assets. The method and system of the present invention provide mechanism for dynamically associating a token with one or more users as owners and one or more assets to track the changes in value of those assets. The monetary value of token is determined using a functional relationship with associated assets. The token can be monetized by users associated with the token as owners in the proportion of their ownership. Monetization of the token represents processing of payments equivalent to the monetary value of the token at the time of monetization.

公开(公告)号：US11321680B2

公开(公告)日：2022-05-03

申请号：US15498465

申请日：2017-04-26

Applicant: Ashish Kumar

Inventor： Ashish Kumar

IPC: G06Q20/06 ,  G06Q20/38 ,  G06Q40/00 ,  G06Q20/32 ,  G06Q20/40 ,  H04L67/306 ,  H04L29/06

Abstract: A method and system for securely processing and managing electronic transactions using one or more electronic currencies. The method and system of the present invention comprise a mechanism for device entities to engage in a financial transaction and process the transaction electronically without being connected to any remote communication link at the time of transaction; any one participating entity of the transaction to submit transaction to a central controller for settlement at any time after the transaction initiation; electronic transaction requiring exchange of electronic currency; electronic currency also being available in physical as well as multiple denominations with localization feature; both electronic transaction and electronic currency to be validated and verified securely through at least one central controller consisting of a central processing unit, operating system software to run the central processing unit and data storage means to identify at least transacting device entities, currency attributes and transaction attributes.