公开(公告)号：US07638415B2

公开(公告)日：2009-12-29

申请号：US12267216

申请日：2008-11-07

申请人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

发明人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/866 ,  H01L21/26506 ,  H01L29/66098

摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括一种制造齐纳二极管的方法，其包括在衬底（210）内形成掺杂阱（240），并在衬底（210）内形成抑制注入（420） ）。 用于制造齐纳二极管的方法还可以包括在衬底（210）内形成阴极（620）和阳极（520），其中抑制注入（420）位于掺杂阱（240）附近，并且被配置为减少穿线 脱臼

公开(公告)号：US20090286371A1

公开(公告)日：2009-11-19

申请号：US12509935

申请日：2009-07-27

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

公开(公告)号：US20090283827A1

公开(公告)日：2009-11-19

申请号：US12120158

申请日：2008-05-13

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

公开(公告)号：US07595525B2

公开(公告)日：2009-09-29

申请号：US11470023

申请日：2006-09-05

申请人： Bill Alan Wofford ,  Blake Ryan Pasker ,  Xinfen Chen ,  Binghua Hu

发明人： Bill Alan Wofford ,  Blake Ryan Pasker ,  Xinfen Chen ,  Binghua Hu

IPC分类号： H01L27/108

CPC分类号： H01L28/40 ,  Y10S438/952

摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

摘要翻译： 公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。 电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。 在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。 薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

公开(公告)号：US07466009B2

公开(公告)日：2008-12-16

申请号：US11422221

申请日：2006-06-05

申请人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

发明人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

IPC分类号： H01L29/93 ,  H01L23/62

CPC分类号： H01L29/866 ,  H01L21/26506 ,  H01L29/66098

摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括制造齐纳二极管的方法，其包括在衬底内形成掺杂阱并在衬底内形成抑制注入。 用于制造齐纳二极管的方法还可以包括在衬底内形成阴极和阳极，其中抑制植入物位于掺杂阱附近并且被配置为减少穿透位错。

公开(公告)号：US06730569B2

公开(公告)日：2004-05-04

申请号：US10001432

申请日：2001-10-25

申请人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

发明人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

IPC分类号： H01L21336

CPC分类号： H01L21/76216

摘要： An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.