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    METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT
    1.
    发明申请
    METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT 有权
    减少使用抑制植入物进行椎间盘切除的方法

    公开(公告)号：US20090061606A1

    公开(公告)日：2009-03-05

    申请号：US12267216

    申请日：2008-11-07

    申请人： MARTIN MOLLAT ,  TATHAGATA CHATTERJEE ,  HENRY L. EDWARDS ,  LANCE S. ROBERTSON ,  RICHARD B. IRWIN ,  BINGHUA HU

    发明人： MARTIN MOLLAT ,  TATHAGATA CHATTERJEE ,  HENRY L. EDWARDS ,  LANCE S. ROBERTSON ,  RICHARD B. IRWIN ,  BINGHUA HU

    IPC分类号： H01L21/265

    CPC分类号： H01L29/866 ,  H01L21/26506 ,  H01L29/66098

    摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

    摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括一种制造齐纳二极管的方法，其包括在衬底（210）内形成掺杂阱（240），并在衬底（210）内形成抑制注入（420） ）。 用于制造齐纳二极管的方法还可以包括在衬底（210）内形成阴极（620）和阳极（520），其中抑制注入（420）位于掺杂阱（240）附近，并且被配置为减少穿线 脱臼

    Method of manufacturing a metal-insulator-metal capacitor using an etchback process
    3.
    发明申请
    Method of manufacturing a metal-insulator-metal capacitor using an etchback process 有权

    公开(公告)号：US20060197134A1

    公开(公告)日：2006-09-07

    申请号：US11071036

    申请日：2005-03-03

    申请人： Tony Phan ,  Martin Mollat

    发明人： Tony Phan ,  Martin Mollat

    IPC分类号： H01L29/94 ,  H01L21/8232

    CPC分类号： H01L27/0629 ,  H01L28/40

    摘要： The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer (185) over a substrate (110), and forming a refractory metal layer (210) having a thickness (t1) over the substrate (110), at least a portion of the refractory metal layer (210) extending over the material layer (185). The method further includes reducing the thickness (t2) of the portion of the refractory metal layer (210) extending over the material layer (185), thereby forming a thinned refractory metal layer (310), and reacting the thinned refractory metal layer (310) with at least a portion of the material layer (185) to form an electrode (440) for use in a capacitor.

    Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor
    4.
    发明申请
    Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor 有权
    具有晶体管级顶侧晶片接点的集成电路及其制造方法

    公开(公告)号：US20070045732A1

    公开(公告)日：2007-03-01

    申请号：US11196087

    申请日：2005-08-03

    申请人： John Lin ,  Tony Phan ,  Philip Hower ,  William Loftin ,  Martin Mollat

    发明人： John Lin ,  Tony Phan ,  Philip Hower ,  William Loftin ,  Martin Mollat

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

    摘要翻译： 本发明提供一种集成电路及其制造方法。 在一个实施例中，集成电路（100）在没有限制的情况下包括位于晶片衬底（110）之上的电介质层（120）和位于电介质层（120）上的半导体衬底（130），半导体衬底 ）具有位于其中或其上的一个或多个晶体管器件（160）。 集成电路（100）还可以包括完全延伸穿过半导体衬底（130）和电介质层（120）的互连（180），从而电接触晶片衬底（110）和一个或多个隔离结构（150） 完全延伸穿过半导体衬底（130）到介电层（120）。

    Method for analyzing critical defects in analog integrated circuits
    5.
    发明申请
    Method for analyzing critical defects in analog integrated circuits 有权
    分析模拟集成电路关键缺陷的方法

    公开(公告)号：US20060171221A1

    公开(公告)日：2006-08-03

    申请号：US11048027

    申请日：2005-01-31

    申请人： Martin Mollat ,  Milind Khandekar ,  Tony Phan ,  Kyle Flessner

    发明人： Martin Mollat ,  Milind Khandekar ,  Tony Phan ,  Kyle Flessner

    IPC分类号： G11C29/00

    CPC分类号： G01R31/2894 ,  G01R31/311

    摘要： The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.

    摘要翻译： 本发明提供了一种用于分析模拟集成电路中的关键缺陷的方法。 用于分析关键缺陷的方法以及其他可能的步骤可以包括对模拟集成电路（115）的功率场效应晶体管（120）部分进行故障测试以获得电气故障数据。 该方法还可以包括执行模拟集成电路（115）的在线光学检查以获得物理缺陷数据，以及将电故障数据和物理缺陷数据相关联以分析关键缺陷。

    Method for reducing dislocation threading using a suppression implant
    6.
    发明授权
    Method for reducing dislocation threading using a suppression implant 有权
    使用抑制植入物减少位错螺纹的方法

    公开(公告)号：US07638415B2

    公开(公告)日：2009-12-29

    申请号：US12267216

    申请日：2008-11-07

    申请人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

    发明人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L29/866 ,  H01L21/26506 ,  H01L29/66098

    摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

    摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括一种制造齐纳二极管的方法，其包括在衬底（210）内形成掺杂阱（240），并在衬底（210）内形成抑制注入（420） ）。 用于制造齐纳二极管的方法还可以包括在衬底（210）内形成阴极（620）和阳极（520），其中抑制注入（420）位于掺杂阱（240）附近，并且被配置为减少穿线 脱臼