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    Method for reducing dislocation threading using a suppression implant
    2.
    发明授权
    Method for reducing dislocation threading using a suppression implant 有权
    使用抑制植入物减少位错螺纹的方法

    公开(公告)号：US07638415B2

    公开(公告)日：2009-12-29

    申请号：US12267216

    申请日：2008-11-07

    申请人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

    发明人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L29/866 ,  H01L21/26506 ,  H01L29/66098

    摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

    摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括一种制造齐纳二极管的方法，其包括在衬底（210）内形成掺杂阱（240），并在衬底（210）内形成抑制注入（420） ）。 用于制造齐纳二极管的方法还可以包括在衬底（210）内形成阴极（620）和阳极（520），其中抑制注入（420）位于掺杂阱（240）附近，并且被配置为减少穿线 脱臼

    Method to manufacture LDMOS transistors with improved threshold voltage control
    4.
    发明授权
    Method to manufacture LDMOS transistors with improved threshold voltage control 有权
    用改进的阈值电压控制制造LDMOS晶体管的方法

    公开(公告)号：US07141455B2

    公开(公告)日：2006-11-28

    申请号：US10712455

    申请日：2003-11-12

    申请人： Binghua Hu ,  Howard S. Lee ,  Henry L. Edwards ,  John Lin ,  Vladimir N. Bolkhovsky

    发明人： Binghua Hu ,  Howard S. Lee ,  Henry L. Edwards ,  John Lin ,  Vladimir N. Bolkhovsky

    IPC分类号： H01L21/332

    CPC分类号： H01L21/266 ,  H01L21/2652 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

    摘要： A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

    摘要翻译： 在外延层（20）中形成双扩散区域（65），（75），（85）。 通过在硬烘烤过程之前首先将诸如硼的光注入物质在光致抗蚀剂层中的开口注入，形成双扩散区域。 在硬烘烤过程之后，可以将诸如砷的重植入物种植入外延层中。 在后续处理（如LOCOS形成）中形成双扩散区。 在外延层（20）上形成介电层（120），并且在电介质层（120）之上形成栅极结构（130），（135）。

    Method to manufacture LDMOS transistors with improved threshold voltage control
    5.
    发明授权
    Method to manufacture LDMOS transistors with improved threshold voltage control 有权
    用改进的阈值电压控制制造LDMOS晶体管的方法

    公开(公告)号：US07696049B2

    公开(公告)日：2010-04-13

    申请号：US11552198

    申请日：2006-10-24

    申请人： Binghua Hu ,  Howard S. Lee ,  Henry L. Edwards ,  John Lin ,  Vladimir N. Bolkhovsky

    发明人： Binghua Hu ,  Howard S. Lee ,  Henry L. Edwards ,  John Lin ,  Vladimir N. Bolkhovsky

    IPC分类号： H01L21/00

    CPC分类号： H01L21/266 ,  H01L21/2652 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

    摘要： A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

    摘要翻译： 在半导体衬底或形成在半导体衬底上的外延层（20）中形成双扩散区域（65），（75），（85）。 通过在硬烘烤过程之前首先将诸如硼的光注入物质在光致抗蚀剂层中的开口注入，形成双扩散区域。 在硬烘烤过程之后，将诸如砷的重注入物质注入到外延层中。 在后续处理中，例如在LOCOS形成期间，通过热退火形成双扩散区域。 在外延层（20）上形成介电层（120），并且在电介质层（120）之上形成栅极结构（130），（135）。

    JFET having width defined by trench isolation
    7.
    发明授权
    JFET having width defined by trench isolation 有权
    JFET具有由沟槽隔离限定的宽度

    公开(公告)号：US09076760B2

    公开(公告)日：2015-07-07

    申请号：US13597439

    申请日：2012-08-29

    申请人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

    发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

    IPC分类号： G01R31/26 ,  H01L29/417 ,  H01L21/00 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10

    CPC分类号： H01L29/41725 ,  G06F2101/00 ,  G06F2201/00 ,  H01L21/00 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/808

    摘要： A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

    摘要翻译： 结型场效应晶体管（JFET）包括具有包括顶侧表面的第一类型半导体表面的衬底和形成在半导体表面中的第二类型的顶栅。 第一型漏极和第一型源形成在顶栅的相对侧上。 第一深沟槽隔离区域具有围绕顶部栅极，漏极和源极的内部第一沟槽壁和外部第一沟槽壁，并且从顶侧表面垂直延伸到深沟槽深度。 形成在半导体表面中的第二类型沉降片在外部第一沟槽壁的外侧横向延伸。 沉降片从顶侧表面垂直延伸到第二类型深部，该深部位于深沟槽深度的下方并且在内部第一沟槽壁的横向内部以提供底部门。

    CMP process for processing STI on two distinct silicon planes
    8.
    发明授权
    CMP process for processing STI on two distinct silicon planes 有权
    用于在两个不同的硅平面上处理STI的CMP工艺

    公开(公告)号：US08551886B2

    公开(公告)日：2013-10-08

    申请号：US12100118

    申请日：2008-04-09

    申请人： Kyle P. Hunt ,  Leila Elvira Noriega ,  Billy Alan Wofford ,  Asadd M. Hosein ,  Binghua Hu ,  Xinfen Chen

    发明人： Kyle P. Hunt ,  Leila Elvira Noriega ,  Billy Alan Wofford ,  Asadd M. Hosein ,  Binghua Hu ,  Xinfen Chen

    IPC分类号： H01L21/302 ,  H01L21/3105

    CPC分类号： H01L21/31051 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/76229 ,  H01L21/76232

    摘要： A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

    摘要翻译： 提供了一种用于半导体处理的方法，其中具有下面的主体的工件和从其延伸的多个特征被提供。 所述多个特征的第一组从下面的本体延伸到第一平面，并且所述多个特征的第二组从下面的本体延伸到第二平面。 保护层覆盖多个特征中的每一个，并且隔离层覆盖下面的主体和保护层，其中隔离具有与其相关联的不均匀的第一氧化物密度。 基于预定图案各向异性蚀刻，然后各向同性蚀刻的隔离层，其中隔离层的第二氧化物密度在整个工件上基本均匀。 该预定图案至少部分地基于期望的氧化物密度，多个特征到第一和第二平面的位置和延伸。

    SINGLE STEP CMP FOR POLISHING THREE OR MORE LAYER FILM STACKS
    9.
    发明申请
    SINGLE STEP CMP FOR POLISHING THREE OR MORE LAYER FILM STACKS 有权
    用于抛光三层或更多层膜片的单步CMP

    公开(公告)号：US20110275168A1

    公开(公告)日：2011-11-10

    申请号：US12776057

    申请日：2010-05-07

    申请人： Eugene C. Davis ,  Binghua Hu ,  Sopa Chevacharoenkul ,  Prakash D. Dev

    发明人： Eugene C. Davis ,  Binghua Hu ,  Sopa Chevacharoenkul ,  Prakash D. Dev

    IPC分类号： H01L21/66 ,  H01L21/306

    CPC分类号： C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

    摘要： A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer>a RR for the silicon oxide layer>a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.

    摘要翻译： 一种用于在其上具有多层膜堆叠的晶片上的三层或更多层膜堆叠的半导体表面上的氮化硅（SiNx）层和SiN x层上的氧化硅层的一步CMP工艺，其中沟槽通孔 延伸穿过硅氧化物层和SiNx层到形成半导体表面的沟槽，并且其中多晶硅层填充沟槽接通通孔，填充沟槽并且在氧化硅层上。 CMP用包括二氧化硅和二氧化铈中的至少一种的浆料颗粒的浆料抛光多层膜堆叠。 CMP提供多晶硅层的去除率（RR）>硅氧化物层的RR> SiNx层的RR。 继续进行CMP处理以去除SiN x层上的多晶硅层，氧化硅层和SiNx层的一部分。 CMP期间的光学终点可以为SiNx层提供预定的剩余厚度范围。

    MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION
    10.
    发明申请
    MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
    具有栅极扩展的MOS晶体管与漏极扩展场绝缘相邻

    公开(公告)号：US20110111569A1

    公开(公告)日：2011-05-12

    申请号：US13006589

    申请日：2011-01-14

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。