公开(公告)号：US20110019458A1

公开(公告)日：2011-01-27

申请号：US12835041

申请日：2010-07-13

Applicant: Cheng Hung Lee ,  Jui-Che Tsai ,  Ching-Wei Wu ,  Kuang Ting Chen

Inventor： Cheng Hung Lee ,  Jui-Che Tsai ,  Ching-Wei Wu ,  Kuang Ting Chen

IPC: G11C5/06

CPC classification number: G11C11/41 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.

Abstract translation: 存储电路包括第一存储器阵列。 第一存储器阵列包括用于存储第一数据的至少一个第一存储器单元。 所述至少一个第一存储单元与第一字线和第二字线耦合。 第二存储器阵列与第一存储器阵列耦合。 第二存储器阵列包括用于存储第二数据的至少一个第二存储器单元。 所述至少一个第二存储单元与第三字线和第四字线耦合。 第一个字线与第三个字线相连。 第一字线在第一存储器阵列中的第一字线的布线方向上与第三字线不对齐。

公开(公告)号：US20100238753A1

公开(公告)日：2010-09-23

申请号：US12716363

申请日：2010-03-03

Applicant: Yen-Huei CHEN ,  Cheng Hung LEE

Inventor： Yen-Huei CHEN ,  Cheng Hung LEE

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

Abstract translation: 集成电路包括用于存储数据的至少一个存储器阵列。 第一开关与存储器阵列耦合。 第一电力线与第一开关耦合。 第一电力线可操作以提供第一电力电压。 第二开关与存储器阵列耦合。 第二电源线与第二开关耦合。 第二电源线可操作以在保持模式期间提供用于保留数据的第二电源电压。 第三电源线与存储器阵列耦合。 第三电源线能够提供第三电源电压。

公开(公告)号：US20090290446A1

公开(公告)日：2009-11-26

申请号：US12126780

申请日：2008-05-23

Applicant: Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

Inventor： Hong-Chen Cheng ,  Hung-Jen Liao ,  Cheng Hung Lee ,  Ruei-Je Tsai

IPC: G11C8/18

CPC classification number: G11C11/18 ,  G11C11/413

Abstract: A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter.

Abstract translation: 一种用于具有多个存储单元的存储器阵列的字线跟踪系统，该字线跟踪系统包括具有与存储器单元的一个或多个规则行基本相同结构的虚拟行，该虚拟行包括一个虚拟字 - 所述线在所述虚拟字线的相对的纵向端具有第一端和第二端，所述第一端连接到字线驱动器，自定时发生器被配置为接收时钟信号并与 用于虚拟字线驱动器的时钟信号，自定时发生器具有用于接收反馈信号以确定脉冲信号的下降沿的第一端子，连接到虚拟字的第二端的电压 - 电流转换器 线路，连接到反馈端子的电流 - 电压转换器以及将电压 - 电流转换器连接到电流 - 电压转换器的导线。

公开(公告)号：US07460391B2

公开(公告)日：2008-12-02

申请号：US11654983

申请日：2007-01-18

Applicant: Cheng Hung Lee ,  Hung-Jen Liao ,  Kun-Lung Chen

Inventor： Cheng Hung Lee ,  Hung-Jen Liao ,  Kun-Lung Chen

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: A semiconductor memory is disclosed, which comprises a plurality of memory cells, at least one high voltage power supply (CVDD) line coupled to the plurality of memory cells for supplying power to the same, and at least one controllable discharging circuit coupled between the CVDD line and a complementary low voltage power supply (ground), wherein only during a write operation the controllable discharging circuit is turned on for discharging the CVDD line.

Abstract translation: 公开了一种半导体存储器，其包括多个存储器单元，耦合到用于向其供电的多个存储单元的至少一个高压电源（CVDD）线以及耦合在CVDD之间的至少一个可控放电电路 线路和互补的低压电源（接地），其中仅在写入操作期间，可控放电电路导通以排出CVDD线。

公开(公告)号：US20080247249A1

公开(公告)日：2008-10-09

申请号：US11732297

申请日：2007-04-03

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C7/06 ,  G01R19/00

CPC classification number: G11C11/4091 ,  G11C5/025

Abstract: A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided.

Abstract translation: 一种电路和方法，用于为控制信号中的失真提供用于DRAM存储器的读出放大器，该读出放大器特别适用于将具有其他逻辑和存储器功能的DRAM存储器嵌入集成电路中。 为具有级联耦合的晶体管对的读出放大器中的差分感测锁存器提供感测使能电路，每个晶体管接收单独的控制信号。 单独的控制信号由具有延迟重叠的控制电路提供。 当分离的控制信号之间存在延迟的重叠时，启用差分感测。 DRAM存储单元的阵列耦合到多个读出放大器。 结合读出放大器的DRAM存储器可以与集成电路中的其它电路嵌入。 提供了提供控制信号和用读出放大器布置DRAM存储器的方法。

公开(公告)号：US20080122525A1

公开(公告)日：2008-05-29

申请号：US11593778

申请日：2006-11-07

Applicant: Cheng-Hung Lee

Inventor： Cheng-Hung Lee

IPC: G05F3/16 ,  G05F3/02

CPC classification number: G11C11/417 ,  G11C5/14

Abstract: This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage booster circuit coupled between a control circuit and the power recipient circuit, wherein the control circuit is configured to turn on-or-off the switching circuit, and to activate or de-activate the voltage booster circuit.

公开(公告)号：US20080106963A1

公开(公告)日：2008-05-08

申请号：US11811659

申请日：2007-06-11

Applicant: Chia Wei Wang ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Fu-Chieh Hsu

Inventor： Chia Wei Wang ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Fu-Chieh Hsu

IPC: G11C7/02 ,  G11C8/00

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.

Abstract translation: 一种电路和方法，用于在具有改进的操作余量的SRAM存储器中的访问周期期间提供两相字线脉冲。 提供第一和第二定时电路，并且提供字线电压抑制电路以减小字线脉冲的第一相中有效字线上的电压，并允许字线上升到第二，未压缩 响应于第一和第二定时电路在字线脉冲的第二相位中的电压。 第一和第二定时电路观察位线电压放电，并且当位线经过某些阈值时提供控制信号有效，这些信号控制电压抑制电路。 因此，SRAM的工作裕度得到改善。 提供了使用两相字线脉冲来操作SRAM的方法。

公开(公告)号：US07313050B2

公开(公告)日：2007-12-25

申请号：US11406984

申请日：2006-04-18

Applicant: Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designating an output of the first inverter and an input of the second inverter, the first inverter having a NMOS transistor with a controllable first source, and a first pull-up circuitry coupled between a positive supply voltage and the first node and selectively activated by a first control signal, wherein when the first source is set to the positive supply voltage and the first control signal is set to a complementary supply voltage of the positive supply voltage, the first node is pulled up to the positive supply voltage to ensure an output of the second inverter is pulled down to the complementary supply voltage.

Abstract translation: 字线驱动器具有来自字线解码器的输入和用于驱动字线的输出。 字线驱动器包括串联连接在输入和输出之间的多个反相器，包括具有指定第一反相器的输出的第一节点和第二反相器的输入的第一和第二反相器，第一反相器具有NMOS 具有可控第一源的晶体管，以及耦合在正电源电压和第一节点之间并由第一控制信号选择性地激活的第一上拉电路，其中当第一源被设置为正电源电压和第一控制信号 设定为正电源电压的互补电源电压，将第一节点上拉至正电源电压，以确保将第二逆变器的输出下拉至互补电源电压。

公开(公告)号：US07215587B2

公开(公告)日：2007-05-08

申请号：US11172873

申请日：2005-07-05

Applicant: Cheng Hung Lee ,  Simon Wang ,  Hung-Jen Liao

Inventor： Cheng Hung Lee ,  Simon Wang ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/419

Abstract: A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.

公开(公告)号：US07190626B2

公开(公告)日：2007-03-13

申请号：US11128846

申请日：2005-05-13

Applicant: Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C17/12 ,  G11C7/12 ,  G11C17/18

Abstract: A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.

Abstract translation: 公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。 存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线， 在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据 锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。