公开(公告)号：US08982609B2

公开(公告)日：2015-03-17

申请号：US13372099

申请日：2012-02-13

申请人： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

发明人： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/4094 ,  G11C11/419

摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

摘要翻译： 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

公开(公告)号：US08958232B2

公开(公告)日：2015-02-17

申请号：US13437081

申请日：2012-04-02

申请人： Jonathan Tsung-Yung Chang ,  Cheng Hung Lee ,  Chung-Cheng Chou ,  Hung-Jen Liao ,  Bin-Hau Lo

发明人： Jonathan Tsung-Yung Chang ,  Cheng Hung Lee ,  Chung-Cheng Chou ,  Hung-Jen Liao ,  Bin-Hau Lo

IPC分类号： G11C17/00

CPC分类号： G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

摘要翻译： 记忆辅助装置包括检测电路和补偿电路。 检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。 如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

公开(公告)号：US08911482B2

公开(公告)日：2014-12-16

申请号：US13418668

申请日：2012-03-13

申请人： Cheng-Hung Lee ,  Chih-Han Chang ,  Chih-Kun Hsiao ,  Kui-Chou Huang ,  Chih-Hui Chen

发明人： Cheng-Hung Lee ,  Chih-Han Chang ,  Chih-Kun Hsiao ,  Kui-Chou Huang ,  Chih-Hui Chen

IPC分类号： A61B17/80 ,  A61B17/58 ,  A61B17/72 ,  A61B17/86

CPC分类号： A61B17/7283 ,  A61B17/8057 ,  A61B17/8061 ,  A61B17/8605 ,  A61B17/8625

摘要： An interlocking bone plate system includes an outer bone plate for being arranged outside a broken bone, an inner bone plate for being installed inside the medullary cavity of the broken bone, and screws for being inserted through and engaged with the outer bone plate and the broken bone and then engaged with the inner bone plate so as to interlock the out and inner bone plates together. The inner bone plate provides an added support in addition to the support provided by the outer bone plate, enhancing the structural strength of the whole bone fixation structure and lowering the risk of failed surgery.

摘要翻译： 互锁骨板系统包括用于布置在骨骨外侧的外骨板，用于安装在破骨的髓腔内部的内骨板，以及用于插入并与外骨板接合的螺钉和破碎的骨 骨，然后与内骨板接合，以将外骨板和内骨板互锁在一起。 内骨板除了外骨板提供的支撑外，还增加了支撑，提高了整个骨固定结构的结构强度，降低了手术失败的风险。

公开(公告)号：US08675439B2

公开(公告)日：2014-03-18

申请号：US13271353

申请日：2011-10-12

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC分类号： G11C5/14

CPC分类号： G11C7/12 ,  G11C11/419

摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

摘要翻译： 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

公开(公告)号：US08634268B2

公开(公告)日：2014-01-21

申请号：US12912971

申请日：2010-10-27

申请人： Cheng Hung Lee ,  Hsu-Shun Chen

发明人： Cheng Hung Lee ,  Hsu-Shun Chen

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C11/418

摘要： The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.

摘要翻译： 本申请公开了一种存储器电路，其具有耦合到第一存储体并被配置为接收多个地址控制信号并且响应于多个地址控制信号产生第一多个小区选择信号的第一解码器， 耦合到第二存储体并且被配置为接收多个反相地址控制信号，并响应于所述多个反相地址控制信号产生第二多个单元选择信号。 存储器电路还具有耦合到第二解码器的地址控制信号缓冲器，并且被配置为将多个地址控制信号转换成多个反相地址控制信号。

公开(公告)号：US20130277794A1

公开(公告)日：2013-10-24

申请号：US13841577

申请日：2013-03-15

申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng-Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng-Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC分类号： H01L23/60

CPC分类号： H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.

摘要翻译： 一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。 包括第二垫的工件被结合到模具。 第一多个微凸块在第一和第二焊盘之间串联电耦合。 多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。 微凸块与模具和工件结合。 第二焊盘电耦合到微凸起。

公开(公告)号：US08519444B2

公开(公告)日：2013-08-27

申请号：US12879447

申请日：2010-09-10

申请人： Annie Lum ,  Derek C. Tao ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Vineet Kumar Agrawal ,  Keun-Young Kim ,  Pyong Yun Cho

发明人： Annie Lum ,  Derek C. Tao ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Vineet Kumar Agrawal ,  Keun-Young Kim ,  Pyong Yun Cho

IPC分类号： H01L27/118

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

摘要翻译： 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

公开(公告)号：US08482990B2

公开(公告)日：2013-07-09

申请号：US13025872

申请日：2011-02-11

申请人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C7/10

CPC分类号： G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

摘要翻译： 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

公开(公告)号：US08406075B2

公开(公告)日：2013-03-26

申请号：US12694032

申请日：2010-01-26

申请人： Cheng Hung Lee ,  Hung-Jen Liao

发明人： Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/063

摘要： An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.

摘要翻译： 集成电路结构包括有源电源线和数据保持电源线。 存储器宏连接到有源电源线和数据保持电源线。 存储器宏包括存储单元阵列和开关。 该开关被配置为在将存储单元阵列连接到有源电源线之间切换连接，并将存储单元阵列连接到数据保持电源线。 数据保持电源线在存储器宏之外。

公开(公告)号：US08385136B2

公开(公告)日：2013-02-26

申请号：US12913087

申请日：2010-10-27

申请人： Cheng Hung Lee ,  Jung-Ping Yang

发明人： Cheng Hung Lee ,  Jung-Ping Yang

IPC分类号： G11C5/14

CPC分类号： G11C7/12 ,  G11C7/067

摘要： The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.

摘要翻译： 本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。 此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。 类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。 存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。