公开(公告)号：US20100027329A1

公开(公告)日：2010-02-04

申请号：US12579695

申请日：2009-10-15

申请人： Charles C. Lee ,  Frank Yu ,  David Q. Chow

发明人： Charles C. Lee ,  Frank Yu ,  David Q. Chow

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C8/06 ,  G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0085 ,  G11C2213/79

摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

摘要翻译： 相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。 存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。 因此，写入时间取决于写入数据并且相对较长。 页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。 主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。 主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。 对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

公开(公告)号：US20080320214A1

公开(公告)日：2008-12-25

申请号：US12186471

申请日：2008-08-05

申请人： Abraham C. Ma ,  David Q. Chow ,  Charles C. Lee ,  Frank Yu

发明人： Abraham C. Ma ,  David Q. Chow ,  Charles C. Lee ,  Frank Yu

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0664 ,  G06F3/0688 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211 ,  G11C13/0004

摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

摘要翻译： 固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。 每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。 磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。 智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。 单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

公开(公告)号：US20080052507A1

公开(公告)日：2008-02-28

申请号：US11838192

申请日：2007-08-13

申请人： David Chow ,  Charles Lee ,  Frank Yu ,  Tzu-Yih Chu ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Frank Yu ,  Tzu-Yih Chu ,  Ming-Shiang Shen

IPC分类号： G06F13/38 ,  G06F1/24 ,  G06F21/00 ,  G06F9/06

CPC分类号： G06F21/568 ,  G06F21/575 ,  G06F2221/2105 ,  G06F2221/2153

摘要： A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.

摘要翻译： 多分区通用串行总线（USB）设备具有具有多个存储分区的闪存。 一些分区用于不同的操作系统并存储操作系统映像。 另一个分区具有控制程序，而用户分区则存储用户数据和用户配置信息。 控制程序可以测试多分区USB设备，并指示主机BIOS将其闪存中的分区作为主机的驱动器安装。 然后可以重新启动主机。 重新启动时，闪存中的OS映像将加载到主内存中，主机使用新的操作系统映像执行新的操作系统。 用户可以按多分区USB设备上的按钮选择要加载的操作系统，并开始重新启动。 备用操作系统中的病毒清除程序可以帮助从主操作系统中的病毒恢复。

公开(公告)号：US20080040598A1

公开(公告)日：2008-02-14

申请号：US11875648

申请日：2007-10-19

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen

IPC分类号： G06F15/177

CPC分类号： G06F9/441

摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.

摘要翻译： 闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。 引导代码包括由闪存微控制器执行的初始引导加载程序，引导代码和控制程序，以及由外部主机执行的操作系统OS映像和外部主机控制程序。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 微控制器在其引导序列期间捕获来自外部主机的第一复位读取地址，并将其与SRAM缓冲器中具有操作系统OS映像和外部主机控制的块的物理地址一起存储在映射表中 程序。 引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。

公开(公告)号：US20070204128A1

公开(公告)日：2007-08-30

申请号：US11742270

申请日：2007-04-30

申请人： Charles Lee ,  Frank Yu ,  David Chow

发明人： Charles Lee ,  Frank Yu ,  David Chow

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.

摘要翻译： 限制性多电平单元（MLC）闪存禁止回归页面写入。 当请求回归页面写入时，找到具有低磨损级别计数的空块，并且按页顺序将存储在旧块中的页面写入的数据和来自页面的页面的数据写入空块。 旧区被擦除并回收。 两级查找表存储在易失性随机存取存储器（RAM）中。 来自主机的逻辑页地址由模分隔器除以生成商和余数。 商是一个逻辑块地址，其索引第一级查找表以找到具有在二级查找表中选择行的物理块地址的映射条目。 剩余部分在二级查找表中的行中找到一列。 如果设置了剩余部分指向的列之上的任何页面有效位，则写入是回归的。

公开(公告)号：US20070156587A1

公开(公告)日：2007-07-05

申请号：US11677658

申请日：2007-02-22

申请人： Frank Yu ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： Frank Yu ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06Q99/00

CPC分类号： G06F21/10

摘要： Content on a storage medium is protected from unauthorized use, such as excessive copying or expired playback. A storage medium contains encrypted content and an encrypted content key with rules such as usage and copy rules. An interface between a record/playback device and the storage medium has enhanced security by not passing unprotected encryption keys that might be intercepted by external hackers. A content key is combined with usage and copy rules and then encrypted with a unique key, and may be doubly-encrypted with a control key before transmission over the interface. The unique key is generated from a key matrix on the record/playback device using row and columns received from the storage medium. The storage medium stores a pre-loaded copy of the unique key. The control key is generated from a random number on the record/playback device and storage medium avoiding transmission over the interface.

摘要翻译： 保护存储介质上的内容免受未经授权的使用，例如过度复制或过期播放。 存储介质包含加密内容和具有诸如使用和复制规则等规则的加密内容密钥。 记录/回放设备和存储介质之间的接口通过不传递可能被外部黑客拦截的未受保护的加密密钥而增强了安全性。 内容密钥与使用和复制规则组合，然后用唯一密钥加密，并且可以在通过接口传输之前用控制密钥进行双重加密。 使用从存储介质接收的行和列从记录/回放设备上的按键矩阵生成唯一密钥。 存储介质存储唯一密钥的预加载副本。 该控制键是从记录/重放设备和存储介质上的随机数生成的，避免了通过接口的传输。

公开(公告)号：US5085239A

公开(公告)日：1992-02-04

申请号：US650854

申请日：1991-02-05

申请人： Teng Chin-Hung ,  Lin-chang Zon ,  Frank Yu

发明人： Teng Chin-Hung ,  Lin-chang Zon ,  Frank Yu

IPC分类号： A45B25/02 ,  A45B25/18

CPC分类号： A45B25/18 ,  A45B25/02

摘要： An umbrella, having a cover stretched over a plastic folding radial frame which comprises upper, intermediate and lower nest plates respectively mounted on a main shaft for securing a plurality of ribs. The nest plates are identical in structure, each comprised an upper circular member having a plurality of pawls and retaining holes at the bottom respectively engaged with a plurality of retaining holes and pawls on the top of a lower circular member for securing the ribs. The cover comprises a plurality of fastening caps at the corners around its periphery and a plurality of snap fastening elements on each radial line thereof for securing the ribs. Because all the parts are made of plastic material, the umbrella is not electrically conductive and can protect against lightning.

摘要翻译： 一种伞，其具有在塑料折叠径向框架上延伸的覆盖物，其包括分别安装在主轴上以固定多个肋的上部，中间和下部嵌板。 巢板的结构相同，每个都包括一个上部圆形构件，其具有多个棘爪，并且底部的保持孔分别与用于固定肋的下部圆形构件的顶部上的多个保持孔和棘爪接合。 该盖包括围绕其周边的拐角处的多个紧固帽和在其每个径向线上的多个卡扣紧固元件，用于固定肋条。 因为所有的部件都是由塑料材料制成，所以伞不导电，可防止闪电。

公开(公告)号：US20120284587A1

公开(公告)日：2012-11-08

申请号：US13540569

申请日：2012-07-02

申请人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

发明人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

IPC分类号： G06F11/16 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0688 ,  G06F12/0868 ,  G06F2212/401 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C11/5678 ,  G11C13/0004 ,  G11C14/0018 ,  G11C29/765

摘要： A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

摘要翻译： 闪存驱动器通过减少对闪存的写入来提高耐用性和使用寿命。 耐久性翻译层（ETL）在DRAM缓冲区中创建，并提供临时存储以减少闪存磨损。 智能存储交换机（SSS）控制器将主机访问分类为内存管理，临时文件，文件分配表（FAT）和文件描述符块（FDB）条目所使用的页面文件以及用户数据文件时，分配数据类型位，使用地址 从FAT读取的范围和文件扩展名。 分页文件和临时文件不会写入闪存。 部分页面数据由通过统一映射表指向的子扇区映射表进行打包和扇区映射，统一映射表将数据类型位和指针存储到DRAM中的数据或表。 部分行业包装在一起，以减少DRAM的使用和闪存磨损。 DRAM中的备用/交换区域可减少闪存磨损。 当纠错失败时，调整参考电压。

公开(公告)号：US08180931B2

公开(公告)日：2012-05-15

申请号：US12651334

申请日：2009-12-31

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F3/0661 ,  G06F3/0613 ,  G06F3/0688 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.

摘要翻译： 电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。 当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。 主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。 设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。 数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

公开(公告)号：US08171204B2

公开(公告)日：2012-05-01

申请号：US12115128

申请日：2008-05-05

申请人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/00

CPC分类号： G06F12/1416 ,  G06F3/0664 ,  G06F12/0851 ,  G06F12/0866 ,  G06F12/0897 ,  G06F21/32 ,  G06F21/78 ,  G06F21/79 ,  G06F2212/2022 ,  Y02D10/13

摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

摘要翻译： 闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。 多级缓存可以减少访问延迟。 电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。 闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。 具有NVMD的闪存系统可能包括用于安全性的指纹读取器。