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    COMPUTER INTERFACE SYSTEM
    61.
    发明申请
    COMPUTER INTERFACE SYSTEM 有权
    计算机接口系统

    公开(公告)号：US20130311436A1

    公开(公告)日：2013-11-21

    申请号：US13475973

    申请日：2012-05-19

    Applicant: Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    Inventor： Jean L. Calvignac ,  Casimer M. DeCusatis ,  Fabrice J. Verplanken ,  Daniel Wind

    IPC: G06F17/30

    CPC classification number: G06F17/00 ,  G06F17/30097 ,  G06F17/3033

    Abstract: An improved computer system may include a controller including a computer processor. The system may also include a selector apparatus in communication with the controller to choose a table having a higher collision quality index than other tables under consideration by the selector apparatus. The system may further include an exchanger apparatus to configure a standby table that replaces the table chosen by the selector apparatus. The system may additionally include a switch that changes a hash function based upon the exchanger apparatus' replacement of the chosen table to enable the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller.

    Abstract translation: 改进的计算机系统可以包括包括计算机处理器的控制器。 该系统还可以包括与控制器通信的选择器装置，以选择具有比选择装置考虑的其它表格更高的冲突质量指标的表格。 该系统还可以包括交换装置，用于配置替换由选择装置选择的表的备用表。 该系统可以另外包括基于交换机设备更换所选择的表来改变散列函数的开关，以使得当与引入控制器的新组件接口时，控制器能够减少插入时间和/或冲突。

    Assignment constraint matrix for assigning work from multiple sources to multiple sinks
    63.
    发明授权
    Assignment constraint matrix for assigning work from multiple sources to multiple sinks 失效
    分配约束矩阵，用于将工作从多个源分配到多个汇点

    公开(公告)号：US08391305B2

    公开(公告)日：2013-03-05

    申请号：US12650080

    申请日：2009-12-30

    Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    IPC: H04L12/28

    CPC classification number: H04L49/9047

    Abstract: An assignment constraint matrix is used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.

    Abstract translation: 分配约束矩阵用于从多个源（例如网络处理设备中的数据队列）向诸如网络处理设备中的处理器线程的多个宿分配诸如数据分组的工作。 分配约束矩阵被实现为适于同时并行操作的多个限定符矩阵。 多个限定符矩阵中的每一个适于确定被支持的源的子集中的源，所述源被限定为基于分配约束向一组接收器提供工作。 合格来源的确定可以是可以在单个芯片上提供用于一组接收器或分布在多个芯片上的接收器可用性信息。

    Data Path for Data Extraction From Streaming Data
    64.
    发明申请
    Data Path for Data Extraction From Streaming Data 有权
    流数据提取数据的数据路径

    公开(公告)号：US20120155492A1

    公开(公告)日：2012-06-21

    申请号：US12974689

    申请日：2010-12-21

    Applicant: Francois Abel ,  Jean L. Calvignac ,  Christoph Hagleitner ,  Jonathan B. Rohrer ,  Jan Van Lunteren ,  Fabrice J. Verplanken

    Inventor： Francois Abel ,  Jean L. Calvignac ,  Christoph Hagleitner ,  Jonathan B. Rohrer ,  Jan Van Lunteren ,  Fabrice J. Verplanken

    IPC: H04J3/24

    CPC classification number: H04J3/1682

    Abstract: A data path for streaming data includes a plurality of sequential data registers, each of the plurality of sequential data registers comprising a plurality of data fields, wherein the streaming data moves sequentially through the sequential data registers; and a multiplexing unit, the multiplexing unit configured such that the multiplexing unit has access to each of the plurality of data fields of the plurality of sequential data registers, and wherein the multiplexing unit is configured to extract data from the streaming data as the streaming data moves through the sequential data registers in response to a data request.

    Abstract translation: 用于流数据的数据路径包括多个顺序数据寄存器，所述多个顺序数据寄存器中的每一个包括多个数据字段，其中所述流数据顺序地通过所述顺序数据寄存器移动; 以及多路复用单元，所述复用单元被配置为使得所述复用单元能够访问所述多个顺序数据寄存器中的所述多个数据字段中的每一个，并且其中所述复用单元被配置为从所述流式数据中提取数据作为所述流数据 响应于数据请求，移动顺序数据寄存器。

    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms
    66.
    发明授权
    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms 有权
    接收具有高效队列流控制，段放置和虚拟化机制的队列设备

    公开(公告)号：US07912988B2

    公开(公告)日：2011-03-22

    申请号：US11487265

    申请日：2006-07-14

    Applicant: William Todd Boyd ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Douglas J. Joseph ,  Renato John Recio

    Inventor： William Todd Boyd ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Douglas J. Joseph ,  Renato John Recio

    IPC: G06F15/16

    CPC classification number: H04L69/16 ,  H04L69/12 ,  H04L69/161

    Abstract: A mechanism for offloading the management of receive queues in a split (e.g. split socket, split iSCSI, split DAFS) stack environment, including efficient queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates receive work queues and completion queues that are utilized by an Internet Protocol Suite Offload Engine (IPSOE) and the ULP to transfer information and carry out send operations. As consumers initiate receive operations, receive work queue entries (RWQEs) are created by the ULP and written to the receive work queue (RWQ). The ISPOE is notified of a new entry to the RWQ and it subsequently reads this entry that contains pointers to the data that is to be received. After the data is received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the RWQ and CQ. The number of entries available in the RWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ.

    Abstract translation: 一种用于卸载分裂（例如，分裂式插座，拆分式iSCSI，拆分式DAFS）堆栈环境中接收队列管理的机制，包括有效的队列流控制和TCP / IP重传支持。 上层协议（ULP）创建互联网协议套件卸载引擎（IPSOE）和ULP利用的接收工作队列和完成队列，以传输信息并执行发送操作。 当消费者开始接收操作时，接收工作队列条目（RWQE）由ULP创建并写入接收工作队列（RWQ）。 通知ISPOE对RWQ的新条目，并随后读取包含要接收的数据的指针的该条目。 接收到数据后，IPSOE创建写入完成队列（CQ）的完成队列条目（CQE）。 在编写CQE之后，ULP随后处理该条目并将其从CQE中移除，释放了RWQ和CQ两者中的空间。 RWQ中可用的条目数由ULP监视，以便它不会覆盖任何有效的条目。 同样，IPSOE监视CQ中可用条目的数量，以免覆盖CQ。

    Full virtualization of resources across an IP interconnect using page frame table
    67.
    发明授权
    Full virtualization of resources across an IP interconnect using page frame table 失效
    使用页面框架表在IP互连中完全虚拟化资源

    公开(公告)号：US07904693B2

    公开(公告)日：2011-03-08

    申请号：US12024773

    申请日：2008-02-01

    Applicant: Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Piyush Chaudhary ,  Edward J. Seminaro

    Inventor： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Piyush Chaudhary ,  Edward J. Seminaro

    IPC: G06F12/10

    CPC classification number: G06F12/10 ,  G06F12/1081 ,  H04L29/12018 ,  H04L61/10

    Abstract: An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.

    Abstract translation: 提供了一种寻址模型，其中包括I / O设备在内的设备通过互联网协议（IP）地址进行寻址，这些地址被认为是虚拟地址空间的一部分。 可以为任务（例如应用程序）分配与虚拟地址空间中的地址对应的有效地址范围。 虚拟地址空间被扩展为包括互联网协议地址。 因此，页框表也被修改为包括用于设备和I / O的IP地址和附加属性的条目。 因此，例如，诸如I / O适配器或甚至打印机的处理元件也可以使用IP地址来寻址，而不需要库调用，设备驱动器，固定存储器等。 该寻址模型还可以跨IP互连提供资源的完全虚拟化，从而允许进程通过网络访问I / O设备。

    Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip
    69.
    发明申请
    Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip 有权
    在单芯片上支持多个高带宽I / O控制器的方法和装置

    公开(公告)号：US20100122011A1

    公开(公告)日：2010-05-13

    申请号：US12270569

    申请日：2008-11-13

    Applicant: Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Daniel M. Dreps ,  Edward J. Seminaro

    Inventor： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Daniel M. Dreps ,  Edward J. Seminaro

    IPC: G06F13/00

    CPC classification number: G06F13/385

    Abstract: An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.

    Abstract translation: 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。

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