公开(公告)号：US06605319B1

公开(公告)日：2003-08-12

申请号：US10074277

申请日：2002-02-11

申请人： Jeffrey D. Chinn ,  Yi-Hsing Chen ,  Robert Z. Bachrach ,  John Christopher Moran

发明人： Jeffrey D. Chinn ,  Yi-Hsing Chen ,  Robert Z. Bachrach ,  John Christopher Moran

IPC分类号： C23C1622

CPC分类号： C23C16/52 ,  C23C16/56

摘要： The method of the invention involves depositing a plurality of thin layers of film, each layer having a thickness ranging from about 500Å to about 2000Å. Low Pressure Chemical Vapor Deposition or other techniques known in the art maybe used to deposit each thin layer of film. The film is polysilicon or silicon-germanium, where the germanium content ranges from about 4% by weight to about 20% by weight germanium. A Rapid Thermal Anneal (“RTA”) is performed on a deposited thin film layer to relieve residual film stress in at least that film layer. The use of RTA rather than furnace annealing permits much shorter annealing times. Optionally, but advantageously, hydrogen may be present during RTA to permit the use of lower processing temperatures, typically about 20% lower relative to a customary anneal. A series of film deposition/rapid thermal anneal cycles is used to produce the desired, nominal total thickness polysilicon film. This method is generally useful for producing polysilicon films in the range of from about 2 microns to about 20 microns.

摘要翻译： 本发明的方法包括沉积多层薄膜，各层的厚度范围为约500至约2000。 低压化学气相沉积或本领域已知的其它技术可以用于沉积每层薄膜。 该膜是多晶硅或硅 - 锗，其中锗含量为约4重量％至约20重量％的锗。 在沉积的薄膜层上进行快速热退火（“RTA”）以减轻至少该膜层中的残余膜应力。 使用RTA而不是炉退火允许更短的退火时间。 可选地，但是有利地，在RTA期间可能存在氢，以允许使用较低的加工温度，相对于常规退火，通常约为20％。 使用一系列膜沉积/快速热退火循环来产生所需的标称总厚度多晶硅膜。 该方法通常可用于生产在约2微米至约20微米范围内的多晶硅膜。

公开(公告)号：US06599437B2

公开(公告)日：2003-07-29

申请号：US09813392

申请日：2001-03-20

申请人： Oranna Yauw ,  Meihua Shen ,  Nicolas Gani ,  Jeffrey D. Chinn

发明人： Oranna Yauw ,  Meihua Shen ,  Nicolas Gani ,  Jeffrey D. Chinn

IPC分类号： H01L213213

CPC分类号： H01L21/0276 ,  H01L21/31138

摘要： A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power. The first source gas and first substrate bias power provide a higher etch rate in dense feature areas than in isolated feature areas during the main etch step, whereas the second source gas and second substrate bias power provide a higher etch rate in isolated feature areas than in dense feature areas during the overetch step, resulting in an overall balancing effect.

摘要翻译： 公开了蚀刻有机涂层，特别是有机抗反射涂层（ARC）层的两步法。 在主蚀刻步骤期间，使用由包括碳氟化合物和非含碳卤素气体的第一源气体产生的等离子体蚀刻有机涂层。 使用第一衬底偏置功率进行蚀刻。 在过蚀刻步骤期间，通过将衬底暴露于由包含含氯气体和含氧气体的第二源气体产生的等离子体而将主蚀刻步骤后剩余的残留有机涂层材料除去，并且不包括 聚合物形成气体。 使用小于第一衬底偏置功率的第二衬底偏置功率来执行过蚀刻步骤。 在主蚀刻步骤期间，第一源气体和第一衬底偏置功率在致密特征区域中提供比在隔离特征区域中更高的蚀刻速率，而第二源气体和第二衬底偏置功率在隔离特征区域中提供比在 在疏浚过程中密集的特征区域，导致整体平衡效果。

公开(公告)号：US06518192B2

公开(公告)日：2003-02-11

申请号：US10013115

申请日：2001-12-07

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

公开(公告)号：US06391788B1

公开(公告)日：2002-05-21

申请号：US09513552

申请日：2000-02-25

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

摘要翻译： 描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。 该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。 该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。 本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。 然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。 还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

公开(公告)号：US06372151B1

公开(公告)日：2002-04-16

申请号：US09362929

申请日：1999-07-27

申请人： Taeho Shin ,  Nam-Hun Kim ,  Jeffrey D. Chinn

发明人： Taeho Shin ,  Nam-Hun Kim ,  Jeffrey D. Chinn

IPC分类号： B44C122

CPC分类号： H01L21/32137

摘要： The method of present invention etches a layer of polysilicon formed on a substrate disposed within a substrate processing chamber. The method flows an etchant gas including sulfur hexafluoride, an oxygen source and a nitrogen source into the processing chamber and ignites a plasma from the etchant gas to etch the polysilicon formed over the substrate. In a preferred embodiment, the etchant gas consists essentially of SF6, molecular oxygen (O2) and molecular nitrogen (N2). In a more preferred embodiment the etchant gas includes a volume ratio of molecular oxygen to the sulfur hexafluoride of between 0.5:1 and 1:1 inclusive and a volume ratio of the sulfur hexafluoride to molecular nitrogen of between 1:1 and 4:1 inclusive. In an even more preferred embodiment, the volume ratio of O2 to sulfur hexafluoride is between 0.5:1 and 1:1 inclusive and the volume ratio of sulfur hexafluoride to N2 is between 1.5:1 and 2:1 inclusive.

摘要翻译： 本发明的方法蚀刻形成在设置在衬底处理室内的衬底上的多晶硅层。 该方法将包括六氟化硫，氧源和氮源的蚀刻剂气体流入处理室，并且从蚀刻剂气体点燃等离子体以蚀刻形成在衬底上的多晶硅。 在优选的实施方案中，蚀刻剂气体基本上由SF 6，分子氧（O 2）和分子氮（N 2）组成。 在更优选的实施方案中，蚀刻剂气体包括分子氧与六氟化硫的体积比在0.5:1至1:1之间，六氟化硫与分子氮的体积比在1:1至4:1之间，包括 。 在更优选的实施方案中，O 2与六氟化硫的体积比在0.5:1和1:1之间，并且六氟化硫与N 2的体积比在1.5:1和2:1之间。

公开(公告)号：US06245684B1

公开(公告)日：2001-06-12

申请号：US09042249

申请日：1998-03-13

申请人： Ganming Zhao ,  Jeffrey D. Chinn

发明人： Ganming Zhao ,  Jeffrey D. Chinn

IPC分类号： H01L21302

CPC分类号： H01L21/31111 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/76232 ,  H01L27/1087

摘要： The present disclosure pertains to our discovery that a particular sequence of processing steps will lead to the formation of a rounded top corner on a trench formed in a semiconductor substrate. In general, the method of the invention includes the following steps: (a) providing a film stack comprising the following layers, from the upper surface of the film stack toward the underlying substrate, (i) a first layer of patterned material which is resistant to a wet etch solution used to etch an underlying second layer and which is resistant to dry etch components used to etch the semiconductor substrate, and (ii) a second layer of material which can be preferentially etched using a wet etch solution, wherein the second layer of material is deposited directly on top of the semiconductor substrate; (b) wet etching the second layer by immersing the film stack in a wet etch solution for a period of time sufficient to form an undercut beneath the first layer and to expose the underlying semiconductor substrate; and (c) isotropically dry etching the exposed semiconductor substrate so as to form a trench in the semiconductor substrate. The present invention provides a method for obtaining a rounded top trench corner while at the same time retaining excellent control of the critical dimensions of the trench. The method of the invention, which is useful in both shallow trench and vertical trench applications, provides a rounded top trench corner having a radius within the range of about 150 Å to about 500 Å, most preferably, within the range of about 200 Å to about 350 Å.

摘要翻译： 本公开涉及我们的发现，即特定的处理步骤序列将导致在半导体衬底中形成的沟槽上形成圆角顶角。 通常，本发明的方法包括以下步骤：（a）从薄膜叠层的上表面朝向下面的基底提供包括以下层的薄膜叠层，（i）第一层图案材料，其具有抗性 涉及用于蚀刻下面的第二层并且耐受用于蚀刻半导体衬底的干蚀刻部件的湿蚀刻溶液，以及（ii）可以使用湿蚀刻溶液优先蚀刻的第二材料层，其中第二层 材料层直接沉积在半导体衬底的顶部; （b）通过将薄膜叠层浸入湿蚀刻溶液中一段时间​​来湿法蚀刻第二层，足以在第一层下方形成底切并露出下面的半导体衬底; 和（c）各向同性干蚀刻暴露的半导体衬底，以便在半导体衬底中形成沟槽。 本发明提供了一种获得圆形顶部沟槽角的方法，同时保持对沟槽的临界尺寸的良好控制。 在浅沟槽和垂直沟槽应用中有用的本发明的方法提供了圆角的顶部沟槽角，其半径在大约至大约的范围内，最优选地在大约至大约的范围内 约350Å。