公开(公告)号：US06270634B1

公开(公告)日：2001-08-07

申请号：US09430798

申请日：1999-10-29

申请人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chinn ,  Dragan Podlesnik

发明人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chinn ,  Dragan Podlesnik

IPC分类号： C23C1434

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/32935 ,  H01L21/3065

摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.

摘要翻译： 本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。 该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。 该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。 在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率 。 另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。 两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。 在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

公开(公告)号：US06372655B2

公开(公告)日：2002-04-16

申请号：US09836934

申请日：2001-04-17

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

公开(公告)号：US06518192B2

公开(公告)日：2003-02-11

申请号：US10013115

申请日：2001-12-07

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

公开(公告)号：US06391788B1

公开(公告)日：2002-05-21

申请号：US09513552

申请日：2000-02-25

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

摘要翻译： 描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。 该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。 该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。 本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。 然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。 还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

公开(公告)号：US06802933B2

公开(公告)日：2004-10-12

申请号：US09740146

申请日：2000-12-18

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： C23F100

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。 该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。 该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。 申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

公开(公告)号：US06318384B1

公开(公告)日：2001-11-20

申请号：US09405349

申请日：1999-09-24

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。 该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。 该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。 申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

公开(公告)号：US06593244B1

公开(公告)日：2003-07-15

申请号：US09659072

申请日：2000-09-11

申请人： Yiqiong Wang ,  Anisul Khan ,  Ajay Kumar ,  Dragan Podlesnik ,  Sharma V. Pamarthy

发明人： Yiqiong Wang ,  Anisul Khan ,  Ajay Kumar ,  Dragan Podlesnik ,  Sharma V. Pamarthy

IPC分类号： H01L21302

CPC分类号： C23F4/00 ,  H01L21/02071 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： A process for etching a pattern-masked conductor substrate anisotropically so as to obtain very high etch rates comprising adding a polymer-forming fluorocarbon gas and an etch gas at high flow rates to an etch chamber at etching pressures of 77 millitorr to 100 Torr using a high source power and bias power to the substrate support electrode to form a high density plasma. The gases can be added together, sequentially or alternately.

摘要翻译： 一种用于各向异性蚀刻图案掩模的导体衬底以便获得非常高的蚀刻速率的方法，包括以77毫微伏至100托的蚀刻压力，将高聚物形成碳氟化合物气体和蚀刻气体以高流速加入蚀刻室， 高源功率和偏置功率到衬底支撑电极以形成高密度等离子体。 气体可以一起，依次或交替地加入。

公开(公告)号：US06303513B1

公开(公告)日：2001-10-16

申请号：US09326334

申请日：1999-06-07

申请人： Anisul Khan ,  Ajay Kumar ,  Dragan V. Podlesnik ,  Jeffrey D. Chinn

发明人： Anisul Khan ,  Ajay Kumar ,  Dragan V. Podlesnik ,  Jeffrey D. Chinn

IPC分类号： H01L2100

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/3299 ,  H01L21/3065

摘要： A method for controlling a profile of a structure formed on a substrate using nitrogen trifluoride (NF3) in a high density plasma (HDP) process. Changing the amount of NF3 in the plasma controls the profile of the structure. It has been found that the best results are obtained with an inductively coupled plasma wherein the ion density is at least 1012 ions/cm3. The method is particularly suited to etch processes such as deep trench etch in silicon wafers.

摘要翻译： 一种用于在高密度等离子体（HDP）工艺中使用三氟化氮（NF 3）在基板上形成的结构的轮廓进行控制的方法。 改变等离子体中NF3的量控制结构的轮廓。 已经发现，使用电感耦合等离子体获得最佳结果，其中离子密度为至少1012离子/ cm3。 该方法特别适用于蚀刻诸如硅晶片中的深沟槽蚀刻的工艺。

公开(公告)号：US06897155B2

公开(公告)日：2005-05-24

申请号：US10219885

申请日：2002-08-14

申请人： Ajay Kumar ,  Anisul H. Khan ,  Dragan Podlesnik ,  Sharma V. Pamarthy ,  Axel Henke ,  Stephan Wege ,  Virinder Grewal

发明人： Ajay Kumar ,  Anisul H. Khan ,  Dragan Podlesnik ,  Sharma V. Pamarthy ,  Axel Henke ,  Stephan Wege ,  Virinder Grewal

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/461

CPC分类号： H01J37/32082 ,  H01J2237/3347 ,  H01L21/3065 ,  H01L21/30655

摘要： A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

摘要翻译： 一种用于操作等离子体反应器以蚀刻真空室中的工件上的高纵横比特征的方法。 该方法包括执行闪光处理之后的蚀刻工艺。 在蚀刻工艺期间，将第一气体供应到真空室中，并且第一气体的等离子体保持第一时间段。 第一气体的等离子体包括蚀刻剂和钝化物质。 在闪蒸过程中，将包含沉积物去除气体的第二气体供应到真空室中，并且将第二气体的等离子体保持第二时间段。 在第二时间段期间，工件与第二气体的等离子体之间的直流电压明显小于在第一时间段内第一气体的工件和等离子体之间的直流电压。

公开(公告)号：US06954561B1

公开(公告)日：2005-10-11

申请号：US09907183

申请日：2001-07-16

申请人： Anisul Khan ,  Ajay Kumar

发明人： Anisul Khan ,  Ajay Kumar

IPC分类号： G02F1/01 ,  G02F1/313 ,  G02B6/12

CPC分类号： G02F1/0147 ,  G02F1/011 ,  G02F1/313

摘要： Thermo-optic devices including a bottom cladding layer, a patterned core material and a top cladding layer, each having a different refractive index, can be made by depositing a heater material, such as tungsten or chromium, on the outside of the bottom and/or top cladding layer. Depending on the refractive index differences between the cladding layers and the core layers, the amount of heater material can also be varied. The heater material can surround the cladding layers, can be present on the sidewalls and top only, or the sidewalls alone, to provide sufficient heat to change the refractive index of the layers and thus the path of light passing-through the device. These devices when built into the substrate can be connected to underlying devices for vertical integration, or connected to other devices and components formed on the same substrate for increased integration.

摘要翻译： 可以通过在底部和/或底部的外侧沉积诸如钨或铬的加热材料来形成包括底部包层，图案化芯材料和折射率不同的顶部包层的热光器件， 或上覆层。 取决于包覆层和芯层之间的折射率差异，加热器材料的量也可以变化。 加热器材料可以围绕包覆层，可以仅存在于侧壁和顶部或单独的侧壁上，以提供足够的热量来改变层的折射率，从而改变穿过该装置的光的路径。 当这些器件内置于基板中时，可以连接到底层器件以进行垂直整合，或者连接到形成在同一衬底上的其他器件和元件，以增加集成度。