公开(公告)号：US08106462B2

公开(公告)日：2012-01-31

申请号：US12687374

申请日：2010-01-14

Applicant: Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

Inventor： Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract translation: 集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。 该对互补晶体管包括第一晶体管和第二晶体管。 该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。 第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。 第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

公开(公告)号：US08063449B2

公开(公告)日：2011-11-22

申请号：US12626496

申请日：2009-11-25

Applicant: Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

Inventor： Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。 移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。 在衬套上形成填充材料。 填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

公开(公告)号：US07947606B2

公开(公告)日：2011-05-24

申请号：US12129479

申请日：2008-05-29

Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

IPC: H01L21/311

CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

公开(公告)号：US07935593B2

公开(公告)日：2011-05-03

申请号：US12366356

申请日：2009-02-05

Applicant: Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

Inventor： Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo implantation masks for both horizontal and vertical PC

Abstract translation: 本公开的实施例在仅使用两个掩模的双嵌入式外延生长（EPI）半导体结构的制造期间提供应力优化，例如用于使用SiC和SiGe的嵌入式外延的nFET和pFET，以及用于水平和垂直PC的分离的晕圈注入掩模

公开(公告)号：US07838372B2

公开(公告)日：2010-11-23

申请号：US12125238

申请日：2008-05-22

Applicant: Jin-Ping Han ,  Jong Ho Yang ,  Chung Woh Lai ,  Henry Utomo

Inventor： Jin-Ping Han ,  Jong Ho Yang ,  Chung Woh Lai ,  Henry Utomo

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在工件的第一区域和第二区域中形成凹陷。 工件的第一区域被掩蔽，并且工件的第二区域中的凹部填充有第一半导体材料。 工件的第二区域被掩蔽，并且工件的第一区域中的凹部填充有第二半导体材料。

公开(公告)号：US20100155854A1

公开(公告)日：2010-06-24

申请号：US12341542

申请日：2008-12-22

Applicant: Knut Stahrenberg ,  Jin-Ping Han

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/28 ,  H01L27/088

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。 图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。 在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压 阈值电压具有与第一阈值电压不同的幅度。

公开(公告)号：US20100136761A1

公开(公告)日：2010-06-03

申请号：US12702443

申请日：2010-02-09

Applicant: Jin-Ping Han

Inventor： Jin-Ping Han

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L29/7834 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract translation: 公开了半导体器件及其制造方法。 优选实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。 第一材料设置在第一区域中，并且第二材料的至少一个区域设置在第一区域内的第一材料内，第二材料包括与第一材料不同的材料。 第二材料的至少一个区域增加第一区域的第一应力。

公开(公告)号：US20090294986A1

公开(公告)日：2009-12-03

申请号：US12129479

申请日：2008-05-29

Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

IPC: H01L23/52 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。