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    Threshold voltage improvement employing fluorine implantation and adjustment oxide layer
    3.
    发明授权
    Threshold voltage improvement employing fluorine implantation and adjustment oxide layer 有权
    使用氟注入和调整氧化物层的阈值电压改善

    公开(公告)号：US07893502B2

    公开(公告)日：2011-02-22

    申请号：US12465908

    申请日：2009-05-14

    申请人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    发明人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807

    摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

    摘要翻译： 可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。 形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。 将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。 在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。 外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

    THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER
    4.
    发明申请
    THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
    使用荧光植入和调整氧化层的阈值电压改进

    公开(公告)号：US20100289088A1

    公开(公告)日：2010-11-18

    申请号：US12465908

    申请日：2009-05-14

    申请人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    发明人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    IPC分类号： H01L27/088 ,  H01L21/8236

    CPC分类号： H01L21/823807

    摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

    摘要翻译： 可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。 形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。 将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。 在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。 外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

    HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE
    5.
    发明申请
    HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE 有权
    用于半导体/高K绝缘体接口的高压电解铜处理

    公开(公告)号：US20120273894A1

    公开(公告)日：2012-11-01

    申请号：US13094873

    申请日：2011-04-27

    申请人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

    发明人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/7843

    摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

    摘要翻译： 集成电路结构在衬底上包括至少一对互补晶体管。 一对互补晶体管包括第一晶体管和第二晶体管。 此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。 第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。 第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

    High pressure deuterium treatment for semiconductor/high-K insulator interface
    6.
    发明授权
    High pressure deuterium treatment for semiconductor/high-K insulator interface 有权
    用于半导体/高K绝缘子接口的高压氘处理

    公开(公告)号：US08445969B2

    公开(公告)日：2013-05-21

    申请号：US13094873

    申请日：2011-04-27

    申请人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

    发明人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/7843

    摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

    摘要翻译： 集成电路结构在衬底上包括至少一对互补晶体管。 一对互补晶体管包括第一晶体管和第二晶体管。 此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。 第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。 第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

    Structure of static random access memory with stress engineering for stability
    9.
    发明授权
    Structure of static random access memory with stress engineering for stability 有权
    具有应力工程稳定性的静态随机存取存储器的结构

    公开(公告)号：US07471548B2

    公开(公告)日：2008-12-30

    申请号：US11611569

    申请日：2006-12-15

    申请人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    发明人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    IPC分类号： G11C11/412 ,  H01L29/78

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

    摘要： An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

    摘要翻译： 提供了一种集成电路（IC），其包括至少一个静态随机存取存储器（SRAM）单元，其中提高了SRAM单元的性能，但具有良好的稳定性和可写性。 特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 γ比值随着pFET器件性能的降低而增加。 更重要的是，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。 本发明提供一种集成电路（IC），其包括至少一个包含至少一个nFET和至少一个pFET的SRAM单元; 以及位于nFET和pFET上方并与其相邻的连续松弛应力衬垫。

    STRESS ENGINEERING FOR SRAM STABILITY
    10.
    发明申请
    STRESS ENGINEERING FOR SRAM STABILITY 有权
    用于SRAM稳定性的应力工程

    公开(公告)号：US20080142895A1

    公开(公告)日：2008-06-19

    申请号：US11611569

    申请日：2006-12-15

    申请人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    发明人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

    IPC分类号： H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

    摘要： An IC is provided that includes at least one SRAM cell in which the performance of the SRAM cell is enhanced, yet maintaining good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention, solves the above by providing an integrated circuit (IC) that comprises at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.

    摘要翻译： 提供了一种IC，其包括至少一个SRAM单元，其中SRAM单元的性能得到增强，同时保持良好的稳定性和可编写性。 特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 在本发明中，γ比随着pFET器件性能的降低而增加。 此外，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。 本发明通过提供一种包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器的集成电路（IC）来解决上述问题， 以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。