公开(公告)号：US08809958B2

公开(公告)日：2014-08-19

申请号：US13296578

申请日：2011-11-15

Applicant: Henning Haffner ,  Manfred Eller ,  Richard Lindsay

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: H01L27/06

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract translation: 公开了集成电路及其制造和设计方法。 例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。 第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。 基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。 该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

公开(公告)号：US08012821B2

公开(公告)日：2011-09-06

申请号：US12364764

申请日：2009-02-03

Applicant: Choongryul Ryou ,  Seunghwan Lee ,  Jun Yuan ,  Victor Chan ,  Manfred Eller ,  Nam Sung Kim ,  Narasimhulu Kanike ,  Srikanth Balaji Samavedam

Inventor： Choongryul Ryou ,  Seunghwan Lee ,  Jun Yuan ,  Victor Chan ,  Manfred Eller ,  Nam Sung Kim ,  Narasimhulu Kanike ,  Srikanth Balaji Samavedam

IPC: H01L21/8238

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Generating an embedded resistor in a semiconductor device includes forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed above the STI region; etching the silicon layer to yield a polyconductor above the STI region; oxidizing the polyconductor; depositing an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer above the STI region; patterning a transistor gate with a photo-resist mask on another portion of the silicon layer away from the STI region; and etching the silicon layer to yield a transistor structure away from the STI region and a resistor structure above the STI region.

Abstract translation: 在半导体器件中产生嵌入式电阻器包括在衬底中形成浅沟槽隔离（STI）区域; 在STI区和衬底上形成衬垫氧化物; 在衬垫氧化物上沉积硅层; 在设置在STI区域上方的硅层的一部分上形成光刻胶掩模; 蚀刻硅层以在STI区域上方产生多导体; 氧化多导体; 在氧化表面上沉积氧化物材料或金属栅极材料; 在氧化物材料或金属栅极材料上沉积硅层; 在STI区域上方的硅层的一部分上沉积附加的硅; 在硅层的远离STI区域的另一部分上形成具有光致抗蚀剂掩模的晶体管栅极; 并蚀刻硅层以产生远离STI区域的晶体管结构和在STI区域上方的电阻器结构。

公开(公告)号：US07892939B2

公开(公告)日：2011-02-22

申请号：US12043384

申请日：2008-03-06

Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC: H01L21/76 ,  H01L21/311

CPC classification number: H01L21/76262 ,  H01L21/76278

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US07820518B2

公开(公告)日：2010-10-26

申请号：US12129510

申请日：2008-05-29

Applicant: Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

Inventor： Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.

Abstract translation: 公开了制造晶体管和半导体器件的方法及其结构。 在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。 侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。

公开(公告)号：US20100264477A1

公开(公告)日：2010-10-21

申请号：US12830070

申请日：2010-07-02

Applicant: Thomas Schiml ,  Manfred Eller

Inventor： Thomas Schiml ,  Manfred Eller

IPC: H01L27/088 ,  H01L27/08

CPC classification number: H01L21/26586 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0203 ,  H01L27/088

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process.

Abstract translation: 公开了半导体器件及其制造方法。 优选实施例包括提供具有第一取向和至少一个第二取向的工件。 半导体器件在工件的第一取向中使用第一注入工艺注入掺杂剂物质。 使用第二注入工艺在工件的至少一个第二取向中注入掺杂剂物质，其中第二注入工艺不同于第一注入工艺。

公开(公告)号：US20100197106A1

公开(公告)日：2010-08-05

申请号：US12364764

申请日：2009-02-03

Applicant: Choongryul Ryou ,  Seunghwan Lee ,  Jun Yuan ,  Victor Chan ,  Manfred Eller ,  Nam Sung Kim ,  Narasimhulu Kanike ,  Srikanth Balaji Samavedam

Inventor： Choongryul Ryou ,  Seunghwan Lee ,  Jun Yuan ,  Victor Chan ,  Manfred Eller ,  Nam Sung Kim ,  Narasimhulu Kanike ,  Srikanth Balaji Samavedam

IPC: H01L21/76 ,  G06F17/50

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.; etching the silicon layer to yield a polyconductor (PC) disposed substantially above the STI region; oxidizing the PC; depositing at least one of an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the at least one oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer disposed substantially above the STI region; patterning a transistor gate with a photo-resist mask disposed on another portion of the silicon layer disposed substantially away from the STI region; and etching the silicon layer to yield at least one transistor structure disposed substantially away from the STI region and at least one resistor structure disposed substantially above the STI region.

Abstract translation: 提供了一种用于在半导体器件和相关的计算机可读存储介质中产生嵌入式电阻器的方法，所述介质的方法和程序步骤包括在衬底中形成浅沟槽隔离（STI）区域; 在STI区和衬底上形成衬垫氧化物; 在衬垫氧化物上沉积硅层; 在基本上位于STI区域上方的硅层的一部分上形成光刻胶掩模; 蚀刻硅层以产生基本上位于STI区域上方的多导体（PC）; 氧化PC; 在氧化表面上沉积氧化物材料或金属栅极材料中的至少一种; 在所述至少一种氧化物材料或金属栅极材料上沉积硅层; 在基本上位于STI区域上方的硅层的一部分上沉积附加的硅; 图案化具有设置在基本上远离STI区域设置在硅层的另一部分上的光致抗蚀剂掩模的晶体管栅极; 并且蚀刻所述硅层以产生基本上远离所述STI区域布置的至少一个晶体管结构以及基本上设置在所述STI区域上的至少一个电阻器结构。

公开(公告)号：US20100148262A1

公开(公告)日：2010-06-17

申请号：US12336702

申请日：2008-12-17

Applicant: Knut Stahrenberg ,  Karl-Heinz Bach ,  Manfred Eller ,  Roland Hampp ,  Jin-Ping Han ,  O Sung Kwon

Inventor： Knut Stahrenberg ,  Karl-Heinz Bach ,  Manfred Eller ,  Roland Hampp ,  Jin-Ping Han ,  O Sung Kwon

IPC: H01L29/772 ,  H01L21/02

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a resistor in a second region of the workpiece. At least one substance is implanted into the semiconductive material of the gate of the transistor or the resistor so that the semiconductive material is different for the gate of the transistor and the resistor.

Abstract translation: 公开了电阻器，半导体器件及其制造方法。 在一个实施例中，制造电阻器的方法包括在工件上形成半导体材料，并且至少构图半导体材料，在工件的第一区域中形成晶体管的栅极，并在第二区域中形成电阻器 工件。 将至少一种物质注入到晶体管或电阻器的栅极的半导体材料中，使得半导体材料对于晶体管和电阻器的栅极是不同的。

公开(公告)号：US20090042359A1

公开(公告)日：2009-02-12

申请号：US11836008

申请日：2007-08-08

Applicant: Richard Lindsay ,  Yong Meng Lee ,  Manfred Eller

Inventor： Richard Lindsay ,  Yong Meng Lee ,  Manfred Eller

IPC: H01L21/71 ,  H01L29/00

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/76237 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.

Abstract translation: 公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓 半导体体。 随后，隔离沟槽填充有电介质材料。

公开(公告)号：US07449374B2

公开(公告)日：2008-11-11

申请号：US11710382

申请日：2007-02-23

Applicant: Matthias Hierlemann ,  Chun-Yung Sung ,  Brian J. Greene ,  Manfred Eller

Inventor： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian J. Greene ,  Manfred Eller

IPC: H01L21/84

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/78

Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

Abstract translation: 集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向旋转5至40度的角度定向在基板上。 诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。 对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

公开(公告)号：US20060202277A1

公开(公告)日：2006-09-14

申请号：US11076080

申请日：2005-03-09

Applicant: Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

Inventor： Matthias Hierlemann ,  Chun-Yung Sung ,  Brian Greene ,  Manfred Eller

IPC: H01L29/94

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/78

Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

Abstract translation: 集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向在0至45度之间旋转的角度定向在基板上。 诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。 对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。