公开(公告)号：US20130272510A1

公开(公告)日：2013-10-17

申请号：US13912422

申请日：2013-06-07

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: H04M3/493

CPC classification number: H04M3/493 ,  H04M3/4931 ,  H04M15/06 ,  H04M2203/254

Abstract: Method of using a computerized smart phone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. When the caller uses the smart phone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smart phone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smart phone can then retrieve at least some of the menu structure of the auto attendant telephony system through this data channel. This application software can then display at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smart phone synchronized with the audio delivery of the menu structure, facilitating interactions with the auto attendant system.

Abstract translation: 使用计算机智能手机导航具有菜单结构的远程自动话务员电话系统的方法。 自动助理的菜单结构放在一个在线计算机数据库中。 当呼叫者使用智能电话与远程自动话务员电话系统（使用该系统的电话号码）呼叫并建立语音信道时，在呼叫者的智能电话通信设备上运行的软件应用程序拦截电话号码以及语音信道 ，也建立与在线计算机可访问数据库的数据通道。 呼叫者的智能手机可以通过该数据信道来检索自动话务员电话系统的至少一些菜单结构。 该应用软件然后可以在与菜单结构的音频传送同步的用户智能电话的图形用户界面上显示远程自动话务员电话系统的至少一些菜单结构，从而促进与自动助理系统的交互。

公开(公告)号：US08549275B2

公开(公告)日：2013-10-01

申请号：US12911640

申请日：2010-10-25

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: H04L29/02 ,  G06F21/22

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602 ,  G06F21/78 ,  G06F2221/2107 ,  G06F2221/2125

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract translation: 能够安全执行的处理器。 该处理器包含一个执行单元和安全的分区逻辑，将分区保存在内存中。 处理器还包含耦合到执行单元的加密逻辑，其加密和解密安全数据和代码。

公开(公告)号：US20130124831A1

公开(公告)日：2013-05-16

申请号：US13730842

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benney Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20130124364A1

公开(公告)日：2013-05-16

申请号：US13325291

申请日：2011-12-14

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06Q30/06

CPC classification number: G06Q30/06 ,  G06Q20/385

Abstract: A computerized method of payment based on short, temporary, transaction ID numbers which protect the security of the payer's (customer's) financial accounts. The payee will first register a source of funds and a payer device with a unique ID (such as a mobile phone and phone number) with the invention's payment server. Then once a payee (merchant) and the payer have agreed on a financial transaction amount, the payee requests a transaction ID from the payment server for that amount. The payment server sends the payee a transaction ID, which the payee then communicates to the payer. The payer in turn relays this transaction ID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server can preserve all records for auditing purposes, but security is enhanced because the merchant never gets direct access to the customer's financial account information.

Abstract translation: 基于短暂，临时，交易ID号码的计算机化付款方式，保护付款人（客户）的财务账户的安全。 收款人将首先使用发明的付款服务器注册资金来源和具有唯一ID（如手机和电话号码）的付款人设备。 然后一旦收款人（商家）和付款人已经同意了金融交易金额，收款人就从付款服务器请求该金额的交易ID。 付款服务器向收款人发送交易ID，收款人然后与付款人进行通信。 付款人又将此交易ID中继到服务器，该服务器使用付款人设备验证交易。 服务器然后向收款人发放资金。 服务器可以保留所有记录以进行审计，但是由于商家无法直接访问客户的财务帐户信息，因此安全性得到增强。

公开(公告)号：US20130091190A1

公开(公告)日：2013-04-11

申请号：US13633086

申请日：2012-10-01

Applicant: Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

Inventor： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

IPC: G06F7/60

CPC classification number: G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US20110131402A1

公开(公告)日：2011-06-02

申请号：US12977459

申请日：2010-12-23

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F15/177

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602 ,  G06F21/78 ,  G06F2221/2107 ,  G06F2221/2125

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

公开(公告)号：US20110093682A1

公开(公告)日：2011-04-21

申请号：US12975807

申请日：2010-12-22

Applicant: ALEXANDER PELEG ,  YAAKOV YAARI ,  MILLIND MITTAL ,  LARRY M. MENNEMEIER ,  BENNY EITAN

Inventor： ALEXANDER PELEG ,  YAAKOV YAARI ,  MILLIND MITTAL ,  LARRY M. MENNEMEIER ,  BENNY EITAN

IPC: G06F15/80 ,  G06F9/02

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。 从第一源寄存器接收第一打包数据元素和第二打包数据元素。 从第二源寄存器接收第三打包数据元素和第四打包数据元素。 所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分 从第三个打包的数据元素。

公开(公告)号：US07596634B2

公开(公告)日：2009-09-29

申请号：US10352800

申请日：2003-01-27

Applicant: Millind Mittal ,  Murali Repakula

Inventor： Millind Mittal ,  Murali Repakula

IPC: G06F15/16

CPC classification number: H04L29/06 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/165

Abstract: Offloading application level communication functions from a host processor. The offloading apparatus can be configured as either a pre-processor or as a co-processor. An interface is provided for receiving a network message sent to the host. An engine performs processing of the network message above OSI level 4. In one embodiment, in a fast-path, a response to the message is sent back to the network without any involvement by the host, providing a complete offload. For other messages, certain pre-processing can be performed, such as parsing of a header, message authentication, and look-up of meta-data. The results of the look-up are then passed to the host with the processed header, simplifying the tasks the host needs to perform. The messages and data are transferred to the host using control and data buffers.

Abstract translation: 从主机处理器卸载应用程序级通信功能。 卸载装置可以被配置为预处理器或协处理器。 提供了一个用于接收发送到主机的网络消息的接口。 引擎执行OSI级别4之上的网络消息的处理。在一个实施例中，在快速路径中，对消息的响应被发送回网络而不需要主机的任何参与，从而提供完整的卸载。 对于其他消息，可以执行某些预处理，例如分析报头，消息认证和元数据查找。 然后将查找结果传递给具有处理头的主机，从而简化了主机执行的任务。 消息和数据使用控制和数据缓冲区传输到主机。

公开(公告)号：US07461109B2

公开(公告)日：2008-12-02

申请号：US11758767

申请日：2007-06-06

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 中央处理单元（CPU）的一个实施例包括提取单指令多数据（SIMD）移位指令的指令提取逻辑。 寄存器存储通过SIMD移位指令来操作的多个数据元素。 桶形移位器响应于SIMD移位指令，同时将数据元素按比特方式移位可变数目的位位置。

公开(公告)号：US07430560B1

公开(公告)日：2008-09-30

申请号：US11309160

申请日：2006-07-03

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06F7/00

CPC classification number: G06F17/30961 ,  Y10S707/99942 ,  Y10S707/99943

Abstract: A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D−1 and 2D for maximum compression. Storage requirements are reduced.

Abstract translation: 在多位Trie结构中使用多级压缩步幅表进行查找。 输入查找键被分成包括S位的当前步幅的几个步骤。 通过压缩S位来形成当前步幅表中的有效条目，以形成D位的压缩索引到当前步幅表中。 压缩函数逻辑组合S位以产生D压缩索引位。 前一级表中的条目指向当前步幅表，并具有指示要使用的压缩函数和掩码的字段。 压缩功能可以包括XOR，移位，旋转和多位平均。 而不是存储所有2个SUPER条目，当前步幅被压缩以仅存储2个条目。 理想情况下，当前步幅表中的有效条目的数目在最大压缩之间的2个D-1和2个D / D之间。 存储要求降低。