公开(公告)号：US20150370562A1

公开(公告)日：2015-12-24

申请号：US14311225

申请日：2014-06-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3867

Abstract: A pipelined run-to-completion processor can decode three instructions in three consecutive clock cycles, and can also execute the instructions in three consecutive clock cycles. The first instruction causes the ALU to generate a value which is then loaded due to execution of the first instruction into a register of a register file. The second instruction accesses the register and loads the value into predicate bits in a register file read stage. The predicate bits are loaded in the very next clock cycle following the clock cycle in which the second instruction was decoded. The third instruction is a conditional instruction that uses the values of the predicate bits as a predicate code to determine a predicate function. If a predicate condition (as determined by the predicate function as applied to flags) is true then an instruction operation of the third instruction is carried out, otherwise it is not carried out.

Abstract translation: 流水线运行到完成处理器可以在三个连续的时钟周期中解码三条指令，并且还可以在三个连续的时钟周期内执行指令。 第一条指令使得ALU产生一个值，该值由于执行第一条指令而被加载到寄存器文件的寄存器中。 第二条指令访问寄存器，并将值加载到寄存器文件读取阶段的谓词位。 谓词位在第二条指令被解码的时钟周期之后的下一个时钟周期中被加载。 第三条指令是使用谓词位的值作为谓词代码来确定谓词函数的条件指令。 如果谓词条件（由标记的谓词函数确定）为真，则执行第三条指令的指令操作，否则不执行。

公开(公告)号：US20150317159A1

公开(公告)日：2015-11-05

申请号：US14267362

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30134 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3867

Abstract: A pipelined run-to-completion processor executes a pop stack absolute instruction. The instruction includes an opcode, an absolute pointer value, a flag don't touch bit, and predicate bits. If a condition indicated by the predicate bits is not true, then the opcode operation is not performed. If the condition is true, then the stack of the processor is popped thereby generating an operand A. The absolute pointer value is used to identify a particular register of the stack, and the content of that particular register is an operand B. The arithmetic logic operation specified by the opcode is performed using operand A and operand B thereby generating a result, and the content of the particular register is replaced with the result. If the flag don't touch bit is set to a particular value, then the flag bits (carry flag and zero flag) are not affected by execution of the instruction.

Abstract translation: 流水线运行到完成处理器执行弹出堆栈绝对指令。 该指令包括操作码，绝对指针值，标志不触摸位和谓词位。 如果谓词位指示的条件不为真，则不执行操作码操作。 如果条件为真，则处理器的堆栈被弹出，从而生成操作数A.绝对指针值用于标识堆栈的特定寄存器，并且该特定寄存器的内容是操作数B.算术逻辑 使用操作数A和操作数B执行由操作码指定的操作，从而生成结果，并且将特定寄存器的内容替换为结果。 如果标志不触摸位设置为特定值，则标志位（进位标志和零标志）不受指令执行的影响。

公开(公告)号：US20150237180A1

公开(公告)日：2015-08-20

申请号：US14184455

申请日：2014-02-19

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber ,  Steven W. Zagorianakos ,  Gavin J. Stark

IPC: H04L29/08 ,  H04L12/801

CPC classification number: H04L69/324 ,  H04L47/34 ,  H04L47/50 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/22

Abstract: Circuitry to provide in-order packet delivery. A packet descriptor including a sequence number is received. It is determined in which of three ranges the sequence number resides. Depending, at least in part, on the range in which the sequence number resides it is determined if the packet descriptor is to be communicated to a scheduler which causes an associated packet to be transmitted. If the sequence number resides in a first “flush” range, all associated packet descriptors are output. If the sequence number resides in a second “send” range, only the received packet descriptor is output. If the sequence number resides in a third “store and reorder” range and the sequence number is the next in-order sequence number the packet descriptor is output; if the sequence number is not the next in-order sequence number the packet descriptor is stored in a buffer and a corresponding valid bit is set.

Abstract translation: 电路提供按顺序分组传送。 接收包括序列号的分组描述符。 确定序列号所在的三个范围中的哪一个。 至少部分地依赖于序列号所在的范围，确定分组描述符是否被传送到导致相关分组被发送的调度器。 如果序列号位于第一个“刷新”范围内，则输出所有关联的数据包描述符。 如果序列号位于第二个“发送”范围内，则仅输出接收到的包描述符。 如果序列号位于第三个“存储和重新排序”范围，并且序列号是下一个顺序序列号，则输出数据包描述符; 如果序列号不是下一个顺序序列号，则分组描述符被存储在缓冲器中并且相应的有效位被置位。

公开(公告)号：US20150222513A1

公开(公告)日：2015-08-06

申请号：US14172851

申请日：2014-02-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: H04L12/26

CPC classification number: H04L41/0866 ,  H04L41/0806 ,  H04L49/65 ,  H04L49/70

Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. For each virtual NID there is a block in a memory of a transactional memory on the NID. This block stores configuration information that configures the corresponding virtual NID. The NID also has a single managing processor that monitors configuration of the plurality of virtual NIDs. If there is a write into the memory space where the configuration information for the virtual NIDs is stored, then the transactional memory detects this write and in response sends an alert to the managing processor. The size and location of the memory space in the memory for which write alerts are to be generated is programmable. The content and destination of the alert is also programmable.

Abstract translation: 网络托管服务器的网络接口设备（NID）实现多个虚拟NID。 对于每个虚拟NID，在NID上的事务存储器的存储器中存在一个块。 该块存储配置相应的虚拟NID的配置信息。 NID还具有监视多个虚拟NID的配置的单个管理处理器。 如果写入存储有虚拟NID的配置信息的存储器空间，则事务存储器检测该写入，并且响应于向管理处理器发送警报。 要生成写入警报的存储器中的存储空间的大小和位置是可编程的。 警报的内容和目的地也是可编程的。

公开(公告)号：US09092284B2

公开(公告)日：2015-07-28

申请号：US14037319

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F21/00 ,  G06F7/58

CPC classification number: G06F7/58

Abstract: An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates.

Abstract translation: 熵存储环包括输入节点，多个串联级和输出节点。 每个级包括XOR（或XNOR）电路，具有耦合到XOR输出的输入的延迟元件，以及具有耦合到XOR的第二输入的输出的组合电路。 组合电路可以是NAND，NOR，或或或门。 XOR的第一个输入是舞台的数据输入。 延迟元件的输出是级的数据输出。 组合电路的第一输入被耦合以从配置寄存器接收使能位。 组合电路的第二输入耦合到环形输出节点。 在操作中，位流被提供到环形输入节点上。 启用多级的反馈，使得位流在其循环时经历复杂的置换。

公开(公告)号：US20150194215A1

公开(公告)日：2015-07-09

申请号：US14151730

申请日：2014-01-09

Applicant: NETRONOME SYSTEMS, INC.

Inventor： Gareth R. Douglas ,  Ciaran J. Toal ,  Sandra Scott-Hayward

IPC: G11C15/04 ,  G06F13/40

CPC classification number: G11C15/04 ,  G06F13/4022 ,  G06F2213/0026 ,  H04L12/462 ,  H04L45/38 ,  H04L45/7453 ,  H04L45/7457 ,  H04L47/21

Abstract: A first packet of a flow received onto an OpenFlow switch causes a flow entry to be added to a flow table, but the associated action is to perform a TCAM lookup. A request is sent to an OpenFlow controller. A response OpenFlow message indicates an action. The response passes through a special dedicated egress fast-path such that the action is applied and the first packet is injected into the main data output path of the switch. A TCAM entry is also added that indicates the action. A second packet of the flow is then received and a flow table lookup causes a TCAM lookup, which indicates the action. The action is applied to the second packet, the packet is output from the switch, and the lookup table is updated so the flow entry will thereafter directly indicate the action. Subsequent packets of the flow do not involve TCAM lookups.

Abstract translation: 接收到OpenFlow交换机上的流的第一个数据包会将流条目添加到流表中，但相关联的操作是执行TCAM查找。 请求被发送到OpenFlow控制器。 响应OpenFlow消息指示一个动作。 响应通过特殊的专用出口快速路径，使得应用该动作，并且将第一分组注入到交换机的主数据输出路径中。 还添加了一个表示该操作的TCAM条目。 然后接收流的第二个分组，并且流表查找导致指示该动作的TCAM查找。 该动作应用于第二个数据包，数据包从交换机输出，并且更新查找表，因此流入口随后将直接指示该动作。 流的后续数据包不涉及TCAM查找。

公开(公告)号：US20150193681A1

公开(公告)日：2015-07-09

申请号：US14151699

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06N5/00 ,  H04L29/08 ,  H04L12/743

CPC classification number: H04L67/10 ,  H04L69/12

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。

公开(公告)号：US20150193483A1

公开(公告)日：2015-07-09

申请号：US14151643

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F17/30

CPC classification number: G06F17/30339 ,  G06F17/30985

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。

公开(公告)号：US20150089096A1

公开(公告)日：2015-03-26

申请号：US14037226

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0683 ,  G06F9/467 ,  H04L49/9031

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

公开(公告)号：US20150088949A1

公开(公告)日：2015-03-26

申请号：US14037303

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F7/58

CPC classification number: G06F7/584

Abstract: A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.

Abstract translation: 具有非确定性熵的比特流由自定时逻辑熵比特流生成器（STLEBSG）产生。 STLEBSG包括一个增量器和一个线性反馈移位寄存器（LFSR），两者均以自定时逻辑实现，作为异步状态机的一部分。 响应于命令，增量器异步地增加一次次数，然后停止，其中次数由命令确定。 对于增量器的每个增量，LFSR经历状态转换。 随着递增器递增，LFSR输出比特流。 如果命令是重复运行命令，则在增量程序停止后，增量程序将重新初始化，然后再次递增次数。 这种递增，停止，重新初始化和递增过程无限期地重复。 另一个命令导致加载器被加载。 另一个命令导致加载LFSR。