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    Method of forming a floating gate in a flash memory device
    61.
    发明授权
    Method of forming a floating gate in a flash memory device 有权
    在闪速存储器件中形成浮动栅极的方法

    公开(公告)号：US06780743B2

    公开(公告)日：2004-08-24

    申请号：US10631200

    申请日：2003-07-31

    Applicant: Sang Wook Park ,  Seung Cheol Lee ,  Jung Il Cho

    Inventor： Sang Wook Park ,  Seung Cheol Lee ,  Jung Il Cho

    IPC: H01L218247

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: Disclosed is a method of forming a floating gate in a date flash memory device on which first and second polysilicon films are stacked. After the first polysilicon film is formed, a SiH4 gas is introduced to decompose SiH4 and SiO2 into Si and H2 and Si and O2. A N2 anneal process is then implemented so that the decomposed H2 gas and O2 gas react to a N2 gas and are then outgassed. Next, a SiH4 gas and a PH3 gas are introduced to form the second polysilicon film. A native oxide film within the interface of the first polysilicon film and the second polysilicon film is removed to improve characteristics of the data flash memory device.

    Abstract translation: 公开了在第一和第二多晶硅膜堆叠的日期闪存器件中形成浮置栅极的方法。 在形成第一多晶硅膜之后，引入SiH 4气体以将SiH 4和SiO 2分解成Si和H 2以及Si和O 2。 然后实施N2退火工艺，使得分解的H 2气体和O 2气体与N 2气体反应，然后脱气。 接着，引入SiH 4气体和PH 3气体，形成第二多晶硅膜。 在第一多晶硅膜和第二多晶硅膜的界面内的自然氧化膜被去除以改善数据闪存器件的特性。

    Method for fabricating flash memory device
    62.
    发明授权
    Method for fabricating flash memory device 有权

    公开(公告)号：US06630392B2

    公开(公告)日：2003-10-07

    申请号：US10029939

    申请日：2001-12-31

    Applicant: Dong Jin Kim ,  Seung Cheol Lee

    Inventor： Dong Jin Kim ,  Seung Cheol Lee

    IPC: H01L21336

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11543

    Abstract: A method for fabricating a flash memory device begins with forming in sequence a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, a control gate, and a hard mask nitride layer on a silicon substrate. The hard mask nitride layer, the control gate, the ONO layer, and the floating gate are then patterned in sequence. Next, a sealing nitride layer is formed on a lateral side of the patterned structure. Also, in order to form a spacer, a first insulating layer is deposited on an entire resultant structure and then selectively patterned. Thereafter, second, third and fourth insulating layers are formed in sequence on the entire resultant structure including the spacer, and a photo resist pattern is then formed on the fourth insulating layer to define a metal contact area.

    Method of manufacturing storage electrode in semiconductor device
    63.
    发明授权
    Method of manufacturing storage electrode in semiconductor device 失效
    在半导体器件中制造存储电极的方法

    公开(公告)号：US06348377B2

    公开(公告)日：2002-02-19

    申请号：US09867602

    申请日：2001-05-31

    Applicant: Cha Deok Dong ,  Seung Cheol Lee ,  Sang Wook Park ,  Dong Jin Kim

    Inventor： Cha Deok Dong ,  Seung Cheol Lee ,  Sang Wook Park ,  Dong Jin Kim

    IPC: H01L218242

    CPC classification number: H01L28/91 ,  H01L21/76895 ,  H01L28/84

    Abstract: A cylindrical storage electrode in a semiconductor device is manufactured by forming a contact hole in a poly oxide film and by forming a first thin film on the film and in the hole. Next, a core oxide film and an anti-reflective coating film are formed on the first thin film to determine the height of the cylinder. A pattern is then formed by etching the anti-reflective coating film, core oxide film and the first thin film such that the poly oxide film is exposed. A second thin film is formed on the overall resultant structure, and a tungsten silicide layer is formed on the second thin film. Inner and outer walls of the cylinder are then formed by blanket-etching the tungsten silicide film and the second thin film such that the core oxide film is exposed. After the core oxide film is removed, a selective metastable polysilicon (SMPS) process is performed so that different grain growths are generated at the inner and outer walls of the cylinder. A storage electrode is then formed by annealing the cylinder. By depositing an amorphous silicon film on the inner wall of the cylinder-type capacitor and Si-rich tungsten silicide film on the outer wall, the surface area of the inner wall expands through normal SMPS and a rugged tungsten silicide film is formed on the outer wall. Spacing between cells is preserved, while generation of a bridge is prevented.

    Abstract translation: 半导体器件中的圆柱形存储电极通过在多氧化物膜中形成接触孔并在膜上和孔中形成第一薄膜来制造。 接下来，在第一薄膜上形成芯氧化膜和抗反射涂膜，以确定气缸的高度。 然后通过蚀刻抗反射涂膜，芯氧化物膜和第一薄膜使得暴露多晶氧化物膜形成图案。 在总体结构上形成第二薄膜，在第二薄膜上形成硅化钨层。 然后通过对硅化钨膜和第二薄膜进行毯式蚀刻来形成圆筒的内壁和外壁，使得芯氧化膜暴露。 在去除核心氧化物膜之后，进行选择性亚稳态多晶硅（SMPS）工艺，使得在圆筒的内壁和外壁处产生不同的晶粒生长。 然后通过使圆筒退火形成存储电极。 通过在圆筒型电容器的内壁和外壁上的富Si硅化钨膜上沉积非晶硅膜，内壁的表面积通过正常的SMPS膨胀，并且在外部形成坚固的硅化钨膜 壁。 保留了单元间的间隔，同时防止了桥的产生。

    Tuning bolt ground connection structure and RF cavity filter including same
    64.
    发明授权
    Tuning bolt ground connection structure and RF cavity filter including same 有权
    调谐螺栓接地结构和射频腔滤波器包括相同

    公开(公告)号：US08362855B2

    公开(公告)日：2013-01-29

    申请号：US13234923

    申请日：2011-09-16

    Applicant: Seung-Cheol Lee

    Inventor： Seung-Cheol Lee

    IPC: H01P1/208 ,  H01P7/06

    CPC classification number: H01P1/2084

    Abstract: An RF cavity filter is disclosed. The disclosed filter includes: a housing having at least one cavity defined; a cover coupled to an upper portion of the housing; at least one resonator contained within the at least one cavity; at least one hole formed in the cover; at least one grounding bolt configured to be inserted into the hole, having a screw thread formed on a part of an outer perimeter, and having a center hole in a center portion; and at least one tuning bolt inserted into the housing through the center hole along a screw thread formed on an inner perimeter of the center hole, where the grounding bolt has a flange part formed on a lower portion that is in contact with the tuning bolt and a lower portion of the cover.

    Abstract translation: 公开了一种RF空腔滤波器。 所公开的过滤器包括：壳体，其具有限定的至少一个空腔; 盖，其联接到所述壳体的上部; 至少一个谐振器包含在所述至少一个空腔内; 形成在所述盖中的至少一个孔; 至少一个接地螺栓，其构造成插入所述孔中，具有形成在外周的一部分上的螺纹，并且在中心部分具有中心孔; 以及至少一个调音螺栓，其沿着形成在所述中心孔的内周上的螺纹穿过所述中心孔插入所述壳体中，其中所述接地螺栓具有形成在与所述调谐螺栓接触的下部的凸缘部分， 盖的下部。

    WIDEBAND ANTENNA USING COUPLING MATCHING
    68.
    发明申请
    WIDEBAND ANTENNA USING COUPLING MATCHING 审中-公开
    宽带天线使用耦合匹配

    公开(公告)号：US20120026064A1

    公开(公告)日：2012-02-02

    申请号：US13264737

    申请日：2009-04-14

    Applicant: Seung-Cheol Lee ,  Byong-Nam Kim ,  Jong-Ho Jung

    Inventor： Seung-Cheol Lee ,  Byong-Nam Kim ,  Jong-Ho Jung

    IPC: H01Q1/50

    CPC classification number: H01Q9/42 ,  H01Q1/243 ,  H01Q5/335 ,  H01Q5/385 ,  H01Q5/50 ,  H01Q9/16

    Abstract: A wide-band antenna using coupling matching is disclosed. The antenna may include a first conductive element, which is electrically connected with a ground; a second conductive element, which is electrically connected with a power feed point and formed parallel to the first conductive element with a particular distance in-between; and a third conductive element for emitting an RF signal that extends from the first conductive element, where the first conductive element and the second conductive element have a particular length such that progressive waves are generated and sufficient coupling is achieved. According to certain aspects of the present invention, a internal type multi-band antenna having wide-band characteristics can be provided, by using coupling matching for multi-band design.

    Abstract translation: 公开了一种使用耦合匹配的宽带天线。 天线可以包括与地面电连接的第一导电元件; 第二导电元件，其与供电点电连接并且平行于第一导电元件形成在其间具有特定距离; 以及用于发射从所述第一导电元件延伸的RF信号的第三导电元件，其中所述第一导电元件和所述第二导电元件具有特定长度，使得产生逐行波并实现充分的耦合。 根据本发明的某些方面，可以通过使用多频带设计的耦合匹配来提供具有宽带特性的内部型多频带天线。

    Image processing apparatus and method for preventing degradation of image quality when bit format of image is converted
    70.
    发明授权
    Image processing apparatus and method for preventing degradation of image quality when bit format of image is converted 有权
    图像处理装置和方法，用于当图像的位格式转换时防止图像质量的劣化

    公开(公告)号：US07800629B2

    公开(公告)日：2010-09-21

    申请号：US11789702

    申请日：2007-04-25

    Applicant: Seung-Cheol Lee ,  Sang-Bong Lee ,  Joon-Kyu Moon

    Inventor： Seung-Cheol Lee ,  Sang-Bong Lee ,  Joon-Kyu Moon

    IPC: G09G5/00 ,  G09G5/02 ,  H04N11/00 ,  H04N1/46 ,  G03F3/08 ,  G06K9/40 ,  G06K9/32

    CPC classification number: G06T5/009

    Abstract: Provided is an image processing apparatus and method for preventing degradation of image quality occurring when a bit-format of an image is converted. When a raw image is converted to an image having specific color resolution, the image to be converted can maintain an image close to the raw image by obtaining errors between pixels of the raw image and the image to be converted and minimizing the errors between the raw image and the image to be converted using an error diffusion scheme.

    Abstract translation: 提供了一种图像处理装置和方法，用于防止当图像的位格式被转换时出现的图像质量的劣化。 当原始图像被转换为​​具有特定颜色分辨率的图像时，要转换的图像可以通过获得原始图像的像素与要转换的图像之间的误差来保持接近于原始图像的图像，并且最小化原始图像之间的误差 图像和使用误差扩散方案转换的图像。

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