公开(公告)号：US20200257647A1

公开(公告)日：2020-08-13

申请号：US16271015

申请日：2019-02-08

申请人： Arm Limited

发明人： Tushar P. Ringe ,  Jamshed Jalal ,  Anitha Kona ,  Mark David Werkheiser

IPC分类号： G06F13/42 ,  G06F13/20

摘要： A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

公开(公告)号：US10725958B1

公开(公告)日：2020-07-28

申请号：US16271015

申请日：2019-02-08

申请人： Arm Limited

发明人： Tushar P. Ringe ,  Jamshed Jalal ,  Anitha Kona ,  Mark David Werkheiser

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F13/20

摘要： A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

公开(公告)号：US10698825B1

公开(公告)日：2020-06-30

申请号：US16299291

申请日：2019-03-12

申请人： Arm Limited

发明人： Gurunath Ramagiri ,  Ashok Kumar Tummala ,  Mark David Werkheiser ,  Jamshed Jalal ,  Premkishore Shivakumar ,  Paul Gilbert Meyer

IPC分类号： G06F12/00 ,  G06F12/0817 ,  G06F16/901

摘要： In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier. The system-unique identifier is used with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line enabling more cache coherent devices to be supported.

公开(公告)号：US10579526B2

公开(公告)日：2020-03-03

申请号：US15427410

申请日：2017-02-08

申请人： ARM Limited

发明人： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

IPC分类号： G06F12/08 ,  G06F12/0831 ,  G06F13/16

摘要： A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.

公开(公告)号：US10423466B2

公开(公告)日：2019-09-24

申请号：US15296283

申请日：2016-10-18

申请人： ARM Limited

发明人： Ashok Kumar Tummala ,  Jamshed Jalal ,  Paul Gilbert Meyer ,  Dimitrios Kaseridis

IPC分类号： G06F9/46 ,  G06F9/52 ,  G06F9/50 ,  H04L29/06

摘要： A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.

公开(公告)号：US10310979B2

公开(公告)日：2019-06-04

申请号：US16189070

申请日：2018-11-13

申请人： Arm Limited

发明人： Jamshed Jalal ,  Mark David Werkheiser

IPC分类号： G06F12/0815 ,  G06F12/0831

摘要： A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

公开(公告)号：US10185663B2

公开(公告)日：2019-01-22

申请号：US15427409

申请日：2017-02-08

申请人： ARM Limited

发明人： Jamshed Jalal ,  Michael Filippo ,  Bruce James Mathewson ,  Phanindra Kumar Mannava

IPC分类号： G06F12/08 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0831 ,  G06F12/128

摘要： A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. The receiver cache level includes presence determination circuitry for performing a determination as to whether the given data value is present in the at least one bypassed cache level. In response to the determination indicating that the data value is present in the at least one bypassed cache level, one of the at least one bypassed cache level is made to respond to the data access request.