公开(公告)号：US12174753B2

公开(公告)日：2024-12-24

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Klas Magnus Bruce ,  Jamshed Jalal ,  Dimitrios Kaseridis ,  Gurunath Ramagiri ,  Ho-Seop Kim ,  Andrew John Turner ,  Rania Hussein Hassan Mameesh

IPC: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.

公开(公告)号：US20210126877A1

公开(公告)日：2021-04-29

申请号：US17051028

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Phanindra Kumar Mannava ,  Dimitrios Kaseridis

IPC: H04L12/931 ,  G06F13/36 ,  H04L12/801 ,  H04L12/933 ,  H04L12/947

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

公开(公告)号：US11483260B2

公开(公告)日：2022-10-25

申请号：US17051028

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Phanindra Kumar Mannava ,  Dimitrios Kaseridis

IPC: H04L49/50 ,  G06F13/36 ,  H04L47/11 ,  H04L49/15 ,  H04L49/25

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

公开(公告)号：US11119961B2

公开(公告)日：2021-09-14

申请号：US16655403

申请日：2019-10-17

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Dimitrios Kaseridis

IPC: G06F13/00 ,  G06F13/40 ,  G06F12/0811 ,  G06F12/0817 ,  G06F13/16

Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

公开(公告)号：US11200177B2

公开(公告)日：2021-12-14

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James Waugh ,  Dimitrios Kaseridis ,  Klas Magnus Bruce ,  Michael Filippo ,  Joseph Michael Pusdesris ,  Jamshed Jalal

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

公开(公告)号：US10423466B2

公开(公告)日：2019-09-24

申请号：US15296283

申请日：2016-10-18

Applicant: ARM Limited

Inventor： Ashok Kumar Tummala ,  Jamshed Jalal ,  Paul Gilbert Meyer ,  Dimitrios Kaseridis

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/50 ,  H04L29/06

Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.