公开(公告)号：US20150193969A1

公开(公告)日：2015-07-09

申请号：US14605944

申请日：2015-01-26

Applicant: ARM LIMITED

Inventor： Jorn Nystad ,  Aske Simon Christensen

IPC: G06T15/80 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/005 ,  G06T2200/04

Abstract: A graphics processor includes a vertex shader 20 that processes input attribute values from a vertex buffer 26 to generate output vertex shaded attribute values 28 to be used by a rasteriser/fragment shader 22 of the graphics processor when processing an image for display. Vertex shader output attributes for which the vertex shader input attributes that the vertex shader output attribute depends on are defined solely on a per-vertex basis or solely on a per-instance basis are identified. Then, for such vertex shader output attributes, the vertex shader 20 stores, for use by the rasteriser/fragment shader 22 of the graphics processor when processing an image for display, only one copy of the vertex shader output attribute for a given vertex or instance, respectively, irrespective of the number of instances or vertices, respectively, that the output attribute value applies to.

Abstract translation: 图形处理器包括顶点着色器20，该顶点着色器20处理来自顶点缓冲器26的输入属性值，以生成输出顶点着色属性值28，以在图形处理器的光栅化器/片段着色器22处理用于显示的图像时使用。 顶点着色器输出属性，顶点着色器输入属性的顶点着色器输出属性依赖于仅在每顶点基础上或仅在每个实例基础上进行定义。 然后，对于这样的顶点着色器输出属性，当处理用于显示的图像时，顶点着色器20存储供图形处理器的光栅化器/片段着色器22使用，以供给予顶点或实例的顶点着色器输出属性的一个副本 ，分别与输出属性值应用于的实例或顶点的数量无关。

公开(公告)号：US08978038B2

公开(公告)日：2015-03-10

申请号：US13909149

申请日：2013-06-04

Applicant: ARM Limited

Inventor： Andreas Due Engh-Halstvedt ,  Jorn Nystad

IPC: G06F9/46 ,  G06F9/48 ,  G06T1/20

CPC classification number: G06F9/46 ,  G06F9/4881 ,  G06F2209/483 ,  G06F2209/484 ,  G06T1/20 ,  Y02D10/24

Abstract: A thread group generator generates from a received workload a plurality of thread groups. Each thread group consists of a plurality of threads, and at least one thread group has an interthread dependency existing between the plurality of threads. Each thread may be either an active thread whose output is required to form the result data, or a dummy thread required to resolve the inter-thread dependency for one of the active threads but whose output is not required to form the result data. A thread execution unit then executes each thread within a thread group received from the generator by executing a predetermined program. Execution flow modification circuitry is responsive to the received thread group having at least one dummy thread, to cause the unit to selectively omit at least part of the execution of at least one of the plurality of instructions when executing each dummy thread.

Abstract translation: 线程组生成器从接收的工作负载生成多个线程组。 每个线程组由多个线程组成，并且至少一个线程组在多个线程之间存在间间线依赖关系。 每个线程可以是要求其输出来形成结果数据的活动线程，也可以是解决对其中一个活动线程但不需要输出结果数据的线程间依赖性所需的虚拟线程。 线程执行单元然后通过执行预定程序来执行从发生器接收到的线程组内的每个线程。 执行流修改电路响应于具有至少一个虚拟线程的所接收的线程组，以使得当执行每个虚拟线程时，该单元选择性地省略至少一个执行多个指令中的至少一个指令。

公开(公告)号：US20140372731A1

公开(公告)日：2014-12-18

申请号：US13918664

申请日：2013-06-14

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3851

Abstract: A data processing system includes an execution pipeline that includes one or more programmable execution stages which execute execution threads to execute instructions to perform data processing operations. Instructions to be executed by a group of execution threads are first fetched into an instruction cache and then read from the instruction cache for execution by the thread group. When an instruction to be executed by a thread group is present in a cache line in the instruction cache, or is to be fetched into an allocated cache line in the instruction cache, a pointer to the location of the instruction in the instruction cache is stored for the thread group. This stored pointer is then used to retrieve the instruction for execution by the thread group from the instruction cache.

Abstract translation: 数据处理系统包括执行流水线，该执行流水线包括执行执行线程以执行指令以执行数据处理操作的一个或多个可编程执行阶段。 由一组执行线程执行的指令首先被提取到指令高速缓存中，然后从指令高速缓存读取以供线程组执行。 当指令高速缓存中的高速缓存线中存在要由线程组执行的指令，或者将其提取到指令高速缓存中的分配的高速缓存行时，存储指向高速缓存中指令位置的指针 为线程组。 然后，该存储的指针用于从指令高速缓存中检索线程组执行的指令。

公开(公告)号：US20140354682A1

公开(公告)日：2014-12-04

申请号：US13909556

申请日：2013-06-04

Applicant: ARM Limited

Inventor： Frode Heggelund ,  Jorn Nystad

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40

Abstract: A tile-based graphics processing pipeline that uses primitive lists that can encompass plural rendering tiles includes a primitive list reading unit that reads primitive lists for a tile being rendered to determine primitives to be processed for the tile and a rasteriser that rasterises input primitives to generate graphics fragments to be processed. The pipeline further comprises a comparison unit between the primitive list reading unit and the rasteriser that for primitives that have been read from primitive lists that include plural rendering tiles, compares the location of the primitive in the render target to the location of the tile being rendered, and then either sends the primitive onwards to the rasteriser if the comparison determines that the primitive could lie at least partially within the tile, or does not send the primitive to the rasteriser if the comparison determines that the primitive definitely does not lie within the tile.

Abstract translation: 使用可以包含多个渲染瓦片的原始列表的基于瓦片的图形处理流水线包括原始列表读取单元，其读取要渲染的瓦片的原始列表，以确定要为该瓦片处理的图元;以及光栅化器，其将输入图元光栅化以生成 要处理的图形片段。 流水线还包括在原始列表读取单元和光栅器之间的比较单元，对于从包括多个渲染图块的原始列表中读取的图元，将渲染目标中的图元的位置与正在渲染的图块的位置进行比较 ，然后如果比较确定原语可以至少部分地位于瓦片内，则将原始图元发送到光栅化器，或者如果比较确定原始图像绝对不在图块内，则不将原始图像发送到光栅器 。

公开(公告)号：US20140354640A1

公开(公告)日：2014-12-04

申请号：US13907550

申请日：2013-05-31

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Frode Heggelund

IPC: G06T15/00 ,  G06T15/40

CPC classification number: G06T15/40

Abstract: A graphics processing pipeline 1 includes a rasteriser 3 that tests patches representing respective different regions of a render output against the edges of primitives 2 to determine if the primitive at least partially covers the patch and an early depth test stage 4 that performs early depth tests for primitives in respect of patches of the render output that the primitive has been found by the rasteriser at least partially to cover, by using depth test information 5 associated with a patch indicating the number and distribution of different depth value regions associated with the patch to determine the depth value region or regions associated with the patch that the primitive should be depth tested against, and then performing a depth test or tests for the primitive in respect of the respective determined depth value region or regions associated with the patch.

Abstract translation: 图形处理管线1包括光栅化器3，光栅化器3针对图元2的边缘测试表示渲染输出的相应不同区域的片段，以确定原始图案是否至少部分地覆盖贴片以及早期深度测试阶段4，其进行早期深度测试 通过使用与指示与补丁相关联的不同深度值区域的数量和分布的补丁相关联的深度测试信息5来至少部分地覆盖由光栅化器发现的原始图案的渲染输出的补码的原语，以确定 与补片相关联的深度值区域或区域，该基元应该相对于相应的确定的深度值区域或与该补片相关联的区域进行深度测试，然后对基元进行深度测试或测试。

公开(公告)号：US20140310507A1

公开(公告)日：2014-10-16

申请号：US13863599

申请日：2013-04-16

Applicant: ARM Limited

Inventor： Jorn Nystad

IPC: G06F9/445

CPC classification number: G06F9/44521

Abstract: When an OpenCL kernel is to be executed, a bitfield index representation to be used for the indices of the kernel invocations is determined based on the number of bits needed to represent the maximum value that will be needed for each index dimension for the kernel. A bitfield placement data structure 33 describing how the bitfield index representation is partitioned is then prepared together with a maximum value data structure 32 indicating the maximum index dimension values to be used for the kernel. A processor then executes the kernel invocations 36 across the index space indicated by the maximum value data structure 32. A bitfield index representation 35, 37, 38 configured in accordance with the bitfield placement data structure 33 is associated with each kernel invocation to indicate its index.

Abstract translation: 当要执行OpenCL内核时，将根据表示内核每个索引维度所需的最大值所需的位数确定要用于内核调用索引的位域索引表示。 然后，与表示要用于内核的最大索引尺寸值的最大值数据结构32一起准备描述如何分割位域索引表示的位字段布置数据结构33。 然后处理器在由最大值数据结构32指示的索引空间上执行内核调用36.根据位字段布局数据结构33配置的位字段索引表示35,37,38与每个内核调用相关联以指示其索引 。

公开(公告)号：US20140267377A1

公开(公告)日：2014-09-18

申请号：US13845604

申请日：2013-03-18

Applicant: ARM LIMITED

Inventor： Andreas Engh Halstvedt ,  Sean Tristram Ellis ,  Jorn Nystad ,  Sandeep Kakarlapudi

IPC: G06T5/00

CPC classification number: G06T11/40

Abstract: A graphics processing pipeline determines whether respective graphics processing operations, such as respective blends, respective depth tests, etc., to be performed at a stage of the graphics processing pipeline would produce the same result for each sampling point of a set of plural sampling points represented by a fragment being processed by the graphics processing pipeline. If it is determined that respective graphics processing operations would produce the same result for each of the sampling points, then only a single instance of the graphics processing operation is performed and the result of that graphics processing operation is associated with each of the sampling points. The number of instances of the graphics processing operations needed to process the set of plural sampling points which the fragment represents is reduced in comparison to conventional multisampling graphics processing techniques which perform graphics processing operations for fragments on a “per sample” basis. The determination of whether or not the same result would be produced for each sampling point of the set of plural sampling points is facilitated by providing metadata which indicates whether or not fragment data and/or stored sample data for use when processing the sampling points is the same.

Abstract translation: 图形处理流水线确定在图形处理流水线的阶段执行各自的图形处理操作，例如相应的混合，相应的深度测试等，将为一组多个采样点的每个采样点产生相同的结果 由图形处理流水线处理的片段表示。 如果确定相应的图形处理操作将为每个采样点产生相同的结果，则仅执行图形处理操作的单个实例，并且该图形处理操作的结果与每个采样点相关联。 与以“每个样本”为基础对片段执行图形处理操作的传统多采样图形处理技术相比，处理片段表示的多个采样点集合所需的图形处理操作的实例的数量减少了。 通过提供指示是否在处理采样点时使用的片段数据和/或存储的采样数据是否为...的元数据，便于确定是否对该组多个采样点的每个采样点产生相同结果的确定 相同。

公开(公告)号：US20130076761A1

公开(公告)日：2013-03-28

申请号：US13623744

申请日：2012-09-20

Applicant: ARM Limited

Inventor： Sean Ellis ,  Andreas Engh-halstvedt ,  Jorn Nystad

IPC: G06F15/16

CPC classification number: G06F15/16 ,  G06F9/5083 ,  G06T1/20 ,  G06T11/40

Abstract: In a tile-based graphics processing system having plural rendering processors, the set of tiles 31 to be processed to generate an output frame 30 for display is partitioned among the different rendering processors by defining respective tile traversal paths 32, 33, 34, 35 for each rendering processor that start at a tile initially allocated to the processor and that, at least for the initial tiles along the path, traverse to spatially adjacent tiles in the output, and that will traverse every tile to be rendered if followed to their end. The next tile for a given rendering processor to process is then selected as being the next tile along its defined path, unless the next tile in the path has already been processed (or is already being processed) by another rendering processor, in which case the next tile to be allocated to the rendering processor is selected to be a free tile further on in the tile traversal path for that processor.

Abstract translation: 在具有多个渲染处理器的基于瓦片的图形处理系统中，要处理以生成用于显示的输出帧30的瓦片组31在不同的渲染处理器之间通过定义相应的瓦片穿越路径32,33,34,35进行划分，用于 每个渲染处理器从最初分配给处理器的瓦片开始，并且至少对于沿着路径的初始瓦片，遍历输出中的空间相邻的瓦片，并且如果跟随到它们的结尾，则遍历要渲染的每个瓦片。 然后，将待处理的给定渲染处理器的下一个图块选择为沿其定义的路径的下一个图块，除非路径中的下一个图块已经被另一个渲染处理器处理（或已被处理），在这种情况下 将要分配给渲染处理器的下一个瓦片选择为该处理器的瓦片穿越路径中的另外的空闲瓦片。

公开(公告)号：US20250111555A1

公开(公告)日：2025-04-03

申请号：US18477647

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Edvard Fielding ,  Rodolfo Luis Jalabert Castellanos ,  Jorn Nystad

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60

Abstract: When performing texture processing operations in a graphics processing system, for a texture processing operation that requires M input texture data elements from an array of texture data elements, each of the M texture data elements is selected from a different set of texture data elements having a different set of positions within the texture data array. The texture processing operation is then performed using the M texture data elements.

公开(公告)号：US11288850B1

公开(公告)日：2022-03-29

申请号：US17189815

申请日：2021-03-02

Applicant: Arm Limited

Inventor： Jorn Nystad

IPC: G06T11/20 ,  G06T1/20 ,  G06T1/60

Abstract: There is disclosed a method of processing an input set of indices that may contain one or more primitive restarts to determine which indices correspond to complete primitives. A modified version of the set of indices can then be written out that contains complete primitives. In particular this is done by determining, for each index in the set of indices, the index position of the start of a sequence of indices for a sequence of primitives that the index is part of, and then determined from this whether or not the index position corresponds to the start of a complete primitive.