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    DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device
    62.
    发明授权
    DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device 有权

    公开(公告)号：US11513986B1

    公开(公告)日：2022-11-29

    申请号：US16983131

    申请日：2020-08-03

    Applicant: Amazon Technologies, Inc.

    Inventor： Asif Khan

    IPC: G06F13/28 ,  G06F12/06

    Abstract: To improve data throughput and data transfer rate, a contiguous block of host memory can be allocated for data transfers between the host system and an integrated circuit device such as a peripheral component. By using a contiguous block of memory that acts as a circular buffer, the memory address field of memory descriptors can be eliminated because the host system only need to inform the data movement engine of the length of each data transfer. The data movement engine can maintain pointers to keep track of the memory address in the host memory to read from and write to. After each data transfer, the relevant pointer can be incremented by a value corresponding to the length indicated in the memory descriptor for the transfer. As such, it is not necessary for the host system to provide the data movement engine with the memory address of each transfer.

    Broadcasting writes to multiple modules
    66.
    发明授权
    Broadcasting writes to multiple modules 有权

    公开(公告)号：US10649923B1

    公开(公告)日：2020-05-12

    申请号：US16250995

    申请日：2019-01-17

    Applicant: Amazon Technologies, Inc.

    Inventor： Asif Khan ,  Robert Michael Johnson

    IPC: G06F13/16 ,  G06F13/40

    Abstract: A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.

    EXTRACTING DEBUG INFORMATION FROM FPGAS IN MULTI-TENANT ENVIRONMENTS
    68.
    发明申请
    EXTRACTING DEBUG INFORMATION FROM FPGAS IN MULTI-TENANT ENVIRONMENTS 审中-公开

    公开(公告)号：US20190293715A1

    公开(公告)日：2019-09-26

    申请号：US16422725

    申请日：2019-05-24

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Christopher Joseph Pettey ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta

    IPC: G01R31/317 ,  G01R31/3177 ,  G06F11/36 ,  G01R31/28

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

    Configurable logic platform
    69.
    发明授权
    Configurable logic platform 有权

    公开(公告)号：US10223317B2

    公开(公告)日：2019-03-05

    申请号：US15279232

    申请日：2016-09-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

    IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Broadcasting reads to multiple modules
    70.
    发明授权
    Broadcasting reads to multiple modules 有权

    公开(公告)号：US10180919B1

    公开(公告)日：2019-01-15

    申请号：US14983154

    申请日：2015-12-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Robert Michael Johnson ,  Asif Khan

    IPC: G06F13/16 ,  G06F13/40

    Abstract: A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.

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