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公开(公告)号：US20160011450A1
公开(公告)日：2016-01-14
申请号：US14577421
申请日：2014-12-19
Applicant: BOE Technology Group Co., Ltd.
IPC: G02F1/13363 , G02F1/1362 , G09G5/00 , H01L27/32 , H01L51/52 , G02F1/1368 , G02F1/1343
CPC classification number: G02F1/13363 , G02F2001/133631 , G02F2001/134345 , G09G3/20 , G09G5/005 , G09G2300/0426 , G09G2300/0452 , G09G2310/08 , G09G2340/10 , H01L27/3218 , H01L51/5293
Abstract: The present invention discloses a display panel, a displayer and a drive method for an array substrate in a display panel. The display panel comprises a cell substrate and an array substrate. Sub-pixel units of the array substrate are classified into first type of sub-pixel units for displaying an original image and second type of sub-pixel units for displaying an interference image. The outermost side of the cell substrate is provided with a FPR film array, wherein, first FPR films are in correspondence to the first type of sub-pixel units so as to convert emitting light of the first type of sub-pixel units into polarized light in a first direction; and a second FPR film is in correspondence to the second type of sub-pixel units so as to convert emitting light of the second type of sub-pixel units into polarized light in a second direction different from the first direction. The displayer may show the original image as well as the interference image simultaneously, and only wearing glasses for filtering interference image can the user observes the normal original image so as to prevent the original image from being observed by a peeper with his/her naked eyes.
Abstract translation: 本发明公开了一种显示面板，显示器以及显示面板中的阵列基板的驱动方法。 显示面板包括单元基板和阵列基板。 阵列基板的子像素单元分为用于显示原始图像的第一类型的子像素单元和用于显示干涉图像的第二类型的子像素单元。 电池基板的最外侧设置有FPR膜阵列，其中，第一FPR膜对应于第一类型的子像素单元，以将第一类型的子像素单元的光转换成偏振光 在第一个方向 并且第二FPR膜对应于第二类型的子像素单元，以将第二类型的子像素单元的光转换成与第一方向不同的第二方向的偏振光。 显示器可以同时显示原始图像以及干涉图像，只有戴眼镜才能过滤干涉图像，用户可以观察到正常的原始图像，以防止原始图像被窥视者用他/她的裸眼观察 。
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公开(公告)号：US12238976B2
公开(公告)日：2025-02-25
申请号：US18594819
申请日：2024-03-04
Inventor： Jianbo Xian , Chen Xu , Pan Li , Yong Qiao , Xinyin Wu
IPC: G06F3/041 , G06F3/044 , H10K59/121 , H10K59/122 , H10K59/131 , H10K59/35 , H10K59/40
Abstract: The disclosure provides a display panel and a display device. The display panel includes: a base substrate, a transistor array layer, a pixel defining layer, touch electrodes. The area of opening region of first color sub-pixel is smaller than that of opening region of third color sub-pixel, the area of opening region of second color sub-pixel is smaller than that of opening region of third color sub-pixel. An orthogonal projection of second capacitor in first color sub-pixel and an orthogonal projection of touch electrodes have a first auxiliary overlap area, an orthogonal projection of second capacitor in second color sub-pixel and orthogonal projection of the touch electrodes have a second auxiliary overlap area, an orthogonal projection of second capacitor in third color sub-pixel and orthogonal projection of touch electrodes have a third auxiliary overlap area. The first and/or second auxiliary overlap area is larger than the third auxiliary overlap area.
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公开(公告)号：US12027093B2
公开(公告)日：2024-07-02
申请号：US18547883
申请日：2021-12-30
Applicant: BOE Technology Group Co., Ltd.
IPC: G09G3/20
CPC classification number: G09G3/2074 , G09G2300/026 , G09G2300/0452 , G09G2320/0233 , G09G2320/0626 , G09G2330/021 , G09G2360/16
Abstract: A method for compensating display of a spliced screen, including: obtaining a picture to be displayed; obtaining a theoretical brightness gain of at least one sub-display region in a plurality of sub-display regions; obtaining an actual brightness gain of the central region according to the theoretical brightness gain of at least part of the sub-display regions, and obtaining actual brightness gains of a plurality of first nodes in the non-central region according to the theoretical brightness gain of at least part of the sub-display regions; obtaining an actual brightness gain of at least part of the non-central region by using a bilinear interpolation method according to the actual brightness gains of the plurality of first nodes and an actual brightness gain of at least one second node on the central region; and compensating the picture to be displayed based on an actual brightness gain of the picture to be displayed.
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公开(公告)号：US12002422B2
公开(公告)日：2024-06-04
申请号：US17293086
申请日：2020-09-14
Inventor： Hongfei Cheng , Xueguang Hao , Hui Li , Chen Xu , Pan Li
IPC: G09G3/3233 , G09G3/3266 , H10K59/121 , H10K59/123 , H10K59/131 , H01L27/12
CPC classification number: G09G3/3233 , G09G3/3266 , H10K59/1213 , H10K59/123 , H10K59/131 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0202 , G09G2310/0286 , H01L27/124
Abstract: A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels, a first power line and an electrical connection layer on the base substrate. Each sub-pixel includes a pixel circuit, and a plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns along a first direction and a second direction. The sub-pixel is electrically connected with the light-emitting element through the electrical connection layer, and the portion, which is in the display region of the display substrate, of the electrical connection layer is not overlapped with the first power line in a direction perpendicular to the base substrate.
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公开(公告)号：US11985861B2
公开(公告)日：2024-05-14
申请号：US17426985
申请日：2021-03-22
Inventor： Jianbo Xian , Chen Xu , Pan Li , Yong Qiao , Xinyin Wu
IPC: G06F3/041 , G06F3/044 , H10K59/121 , H10K59/122 , H10K59/131 , H10K59/35 , H10K59/40
CPC classification number: H10K59/122 , G06F3/0446 , H10K59/1213 , H10K59/1216 , H10K59/131 , H10K59/353 , H10K59/40
Abstract: The disclosure provides a display panel and a display device. The display panel includes: a base substrate, a transistor array layer, a pixel defining layer, touch electrodes. The area of opening region of first color sub-pixel is smaller than that of opening region of third color sub-pixel, the area of opening region of second color sub-pixel is smaller than that of opening region of third color sub-pixel. An orthogonal projection of second capacitor in first color sub-pixel and an orthogonal projection of touch electrodes have a first auxiliary overlap area, an orthogonal projection of second capacitor in second color sub-pixel and orthogonal projection of the touch electrodes have a second auxiliary overlap area, an orthogonal projection of second capacitor in third color sub-pixel and orthogonal projection of touch electrodes have a third auxiliary overlap area. The first and/or second auxiliary overlap area is larger than the third auxiliary overlap area.
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Patent Agency Ranking
公开(公告)号：US11822196B2
公开(公告)日：2023-11-21
申请号：US16966592
申请日：2019-07-25
Inventor： Hongfei Cheng , Pan Li
IPC: G02F1/1362 , G02F1/1333 , G02F1/1343
CPC classification number: G02F1/136286 , G02F1/13338 , G02F1/134309
Abstract: An array substrate includes at least one driving electrode region and at least one sensing electrode region which are alternately arranged along a row direction and are disconnected from each other, each driving electrode region and each sensing electrode region include one first common electrode and one second common electrode respectively, at least one driving electrode line continuously passes through the driving electrode region and the sensing electrode region alternately arranged along the row direction. The first common electrode in the driving electrode region is connected to the driving electrode line through at least one first through hole, the second common electrode in the sensing electrode region is disconnected from the driving electrode line.
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公开(公告)号：US11276713B2
公开(公告)日：2022-03-15
申请号：US16630738
申请日：2019-04-04
IPC: H01L27/12
Abstract: Arrangements disclosed in the present disclosure provide an array substrate, a manufacturing, a display panel and a display device. The array substrate comprises: a first signal line comprising a first extension portion along a first direction and a first connection portion along a second direction, which is provided with via holes; a second signal line comprising a second extension portion and a second connection portion along the second direction, which is provided with via holes; and a conductive connection layer, configured to connect the first signal line and the second signal line through the via holes of the first connection portion and second connection portion. The first connection portion and the second connection portion are lined up in a direction perpendicular to the second direction.
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公开(公告)号：US11249351B2
公开(公告)日：2022-02-15
申请号：US16882948
申请日：2020-05-26
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jianbo Xian , Pan Li , Yong Qiao , Xinyin Wu , Jian Xu
IPC: G02F1/1343 , G02F1/1362 , H01L27/12 , H01L29/786 , H01L21/02
Abstract: Embodiments of the present disclosure provide an array substrate and a display device. The array substrate includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines crossing one another to bound pixel units and the pixel unites each including a pixel electrode and a thin film transistor, which includes a drain electrode, the array substrate further includes a common electrode line, the drain electrode includes an extension portion and the common electrode line and the extension portion form a light blocking structure together such that an orthographic projection of the light blocking structure on a plane where the pixel electrode is located is located near an edge of the pixel electrode. The array substrate provided by the present disclosure is applied to a display device.
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公开(公告)号：US20220036822A1
公开(公告)日：2022-02-03
申请号：US17278692
申请日：2020-07-30
Inventor： Pan Li , Xueguang Hao , Chen Xu
IPC: G09G3/3233
Abstract: A pixel driving circuit, an array substrate and a display device are provided. The pixel driving circuit includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is arranged on the side of a gate layer lead away from a base substrate and is formed with a first via hole exposing the gate layer lead. The second interlayer dielectric layer is arranged on the side of the first interlayer dielectric layer away from the base substrate and is formed with a second via hole exposing the first via hole. A source drain layer lead is arranged on the side of the second interlayer dielectric layer away from the base substrate and is electrically connected to the gate layer lead through the first via hole and the second via hole.
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公开(公告)号：US11209702B2
公开(公告)日：2021-12-28
申请号：US16184305
申请日：2018-11-08
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Wenbo Li , Xinyin Wu , Pan Li , Hongfei Cheng , Jianbo Xian
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L21/02 , H01L21/443 , H01L27/02 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/285 , H01L29/786
Abstract: The present application discloses an array substrate, a display panel and a display device. The array substrate comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, the pixel unit further comprising: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.
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