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    LDPC (Low Density Parity Check) coded modulation symbol decoding
    62.
    发明申请
    LDPC (Low Density Parity Check) coded modulation symbol decoding 有权
    LDPC（低密度奇偶校验）编码调制符号解码

    公开(公告)号：US20110072336A1

    公开(公告)日：2011-03-24

    申请号：US12957238

    申请日：2010-11-30

    申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

    发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

    IPC分类号： G06F11/00

    CPC分类号： H04L27/2602 ,  G11B20/1833 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/25 ,  H03M13/255 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/4161 ,  H03M13/45 ,  H03M13/6516 ,  H03M13/6583 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/1671 ,  H04L27/18

    摘要： LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

    摘要翻译： LDPC（低密度奇偶校验）编码调制符号解码。 通过适当地修改LDPC三部分图来消除比特节点从而生成LDPC二分图（使得符号节点被适当地映射到校验节点从而消除比特节点）来支持符号解码。 将符号节点通信地耦合到校验节点的边缘被适当地标记以支持LDPC编码调制信号的符号解码。 迭代解码处理可以包括更新校验节点以及估计符号序列和更新符号节点。 在一些实施例中，可以执行替代的混合解码方法，使得执行位电平和符号电平解码的组合。 该LDPC码解码仅执行比特解码。 此外，它提供可比较或更好的比特解码性能，涉及相关度量的迭代更新。

    Partial-parallel implementation of LDPC (Low Density Parity Check) decoders
    63.
    发明授权
    Partial-parallel implementation of LDPC (Low Density Parity Check) decoders 失效
    LDPC（低密度奇偶校验）解码器的部分并行实现

    公开(公告)号：US07661055B2

    公开(公告)日：2010-02-09

    申请号：US11323901

    申请日：2005-12-30

    申请人： Tak K. Lee ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Kelly Brian Cameron

    发明人： Tak K. Lee ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Kelly Brian Cameron

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0052 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/255 ,  H03M13/27 ,  H04L1/0057

    摘要： Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.

    摘要翻译： LDPC（低密度奇偶校验）解码器的部分并行实现。 提出了一种新颖的方法，通过该方法在对LDPC编码信号执行纠错解码时，在每个位节点处理和校验节点处理期间执行所选择的周期数。 每个位节点处理和校验节点处理的周期数不必相同。 可以在比特节点处理和校验节点处理两者期间使用至少一个功能块，组件，硬件部分或计算，从而通过有效利用处理资源来节省空间。 至少可以执行在每个位节点处理和校验节点处理期间执行2个周期的半并行方法。 或者，可以对比特节点处理和校验节点处理中的每一个执行多于2个周期。

    True bit level decoding of TTCM (turbo trellis code modulation) of variable rates and signal constellations
    64.
    发明授权
    True bit level decoding of TTCM (turbo trellis code modulation) of variable rates and signal constellations 有权
    TTCM（Turbo Trellis Code Modulation）的可变速率和信号星座的真实位解码

    公开(公告)号：US07657822B2

    公开(公告)日：2010-02-02

    申请号：US10429362

    申请日：2003-05-01

    申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

    发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

    IPC分类号： H03M13/25 ,  H03M13/29

    CPC分类号： H04L1/005 ,  H03M13/256 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4123 ,  H03M13/4161 ,  H04L1/0055 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    摘要： True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

    摘要翻译： TTCM（Turbo Trellis编码调制）的可变速率和信号星座的真位解码。 提出了一种解码方法，其允许基于比特级的解码，其允许区分符号的各个比特。 而现有技术方法通常在符号级基础上执行解码，这种解码方法允许改进的方法，其中可以针对信息符号的各个比特分别进行硬判决/最佳估计。 此外，解码方法允许减少需要执行的计算的总数以及在迭代解码期间需要存储的值的总数。 比特级解码方法还能够解码其码率和/或信号星座类型（和映射）可以在逐个符号的基础上变化的信号。

    Overlapping sub-matrix based LDPC (low density parity check) decoder
    65.
    发明授权
    Overlapping sub-matrix based LDPC (low density parity check) decoder 失效
    重叠的基于子矩阵的LDPC（低密度奇偶校验）解码器

    公开(公告)号：US07644339B2

    公开(公告)日：2010-01-05

    申请号：US11709078

    申请日：2007-02-21

    申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

    发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1162 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/616 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583

    摘要： Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

    摘要翻译： 提出了新的解码方法，通过该方法，立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息，而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息，而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比，使用这种方法，在给定时间段内可以执行两倍的解码迭代，然后更新整个LDPC矩阵的所有位边消息，以及 所以。 当结合最小和处理执行这种重叠方法时，也可以节省大量的内存。

    Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices
    66.
    发明授权
    Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices 失效
    具有具有CSI（循环移位标识）子矩阵的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码的有效构造

    公开(公告)号：US07617441B2

    公开(公告)日：2009-11-10

    申请号：US11472226

    申请日：2006-06-21

    申请人： Tak K. Lee ,  Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

    发明人： Tak K. Lee ,  Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

    IPC分类号： G06F11/00

    CPC分类号： H03M13/11

    摘要： Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).

    摘要翻译： 具有具有CSI（循环移位身份）子矩阵的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码的高效构造。 这些构造的LDPC码可以在多输入多输出（MIMO）通信系统中实现。 一种LDPC码构造方法使用CSI子矩阵移位值，其移位值被检查，而不是奇偶校验矩阵（或其对应的子矩阵）内的非零元素位置。 当设计LDPC码时，该方法在LDPC码的相应二分图中找到并避免周期（或循环）是有效的。 另一种方法涉及基于GRS（Generalized Reed-Solomon）代码的LDPC码构造。 这些LDPC码可以在各种各样的通信设备中实现，包括在符合由IEEE 802.11n任务组（即正在努力开发的任务组）的建议实践和标准的无线通信系统中实现的通信设备 802.11 TGn（高吞吐量）标准）。

    Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders
    67.
    发明授权
    Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders 有权
    有效的前端存储器布置支持LDPC（低密度奇偶校验）解码器中的并行比特节点和校验节点处理

    公开(公告)号：US07587659B2

    公开(公告)日：2009-09-08

    申请号：US11171727

    申请日：2005-06-30

    申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen

    发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen

    IPC分类号： H03M13/03 ,  H03M13/00

    CPC分类号： H03M13/6563 ,  H03M13/1137 ,  H03M13/1165

    摘要： Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).

    摘要翻译： 有效的前端存储器布置支持LDPC（低密度奇偶校验）解码器中的并行比特节点和校验节点处理。 提出了一种能够对LDPC编码信号进行解码的装置的前端设计有助于LDPC编码信号的并行解码处理的新颖方法。 结合执行度量发生器的前端存储器管理的实现协同地借助于LDPC编码信号的非常有效的并行解码处理。 存在可以实现前端存储器管理和度量生成器以促进LDPC编码信号的这种并行解码处理的几个实施例。 这也允许解码可变码率和/或可变调制信号，其码率和/或调制随着逐个块的频率而变化（例如，一个块可以包括帧内的符号组）。

    Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code
    69.
    发明授权
    Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code 有权
    使用GRS（广义里德 - 所罗门）代码构建LDPC（低密度奇偶校验）码

    公开(公告)号：US07536629B2

    公开(公告)日：2009-05-19

    申请号：US11190333

    申请日：2005-07-27

    申请人： Ba-Zhong Shen ,  Scott Richard Powell ,  Kelly Brian Cameron ,  Hau Thien Tran

    发明人： Ba-Zhong Shen ,  Scott Richard Powell ,  Kelly Brian Cameron ,  Hau Thien Tran

    IPC分类号： H03M12/00

    CPC分类号： H03M13/255 ,  H03M7/30 ,  H03M13/03 ,  H03M13/033 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515

    摘要： Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices implemented within communication systems. This approach may be employed to generate GRS based LDPC codes particular designed for various application arenas. As one example, such a GRS based LDPC code may be specifically designed for use in communication systems that operate in accordance with any standards and/or recommended practices of the IEEE P802.3an (10GBASE-T) Task Force.

    摘要翻译： 使用GRS（广义里德 - 所罗门）代码构建LDPC（低密度奇偶校验）码。 提出了一种新颖的方法，通过该方法可以采用GRS代码来生成各种各样的LDPC码。 这种基于GRS的LDPC码可以在通信系统内实现的各种类型的收发信机中使用。 可以采用该方法来生成针对各种应用领域特别设计的基于GRS的LDPC码。 作为一个示例，这样的基于GRS的LDPC码可以专门设计用于根据IEEE P802.3an（10GBASE-T）任务组的任何标准和/或推荐做法进行操作的通信系统。