Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
    62.
    发明授权
    Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering 有权
    通过栅极应力工程在体硅和SOI CMOS器件中的无位错应力通道

    公开(公告)号:US07504693B2

    公开(公告)日:2009-03-17

    申请号:US10709239

    申请日:2004-04-23

    摘要: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

    摘要翻译: 公开了通过具有SiGe和/或Si:C的栅极应力工程的体硅和SOI(绝缘体上硅)CMOS(互补金属氧化物半导体)器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底,衬底上的栅极介电层,以及SiGe和/或Si:C的层叠栅极结构,其具有在SSi(应变Si)/ SiGe或SSi的界面处产生的应力 / Si:C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层,在第一应力膜层上的应变SiGe或应变Si:C的第二应力膜层,以及半导体或导体 p(聚)-Si在第二应力膜层上。

    STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS
    64.
    发明申请
    STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS 失效
    用混合晶体取向和不同应力水平制造具有应力的硅直接绝缘体衬底的结构和方法

    公开(公告)号:US20080296634A1

    公开(公告)日:2008-12-04

    申请号:US12192573

    申请日:2008-08-15

    IPC分类号: H01L29/04 H01L29/00

    摘要: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

    摘要翻译: 本发明提供了具有多个结晶取向的应变Si直接绝缘体(SSDOI)基板及其形成方法。 广义上,但是具体来说,本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层,所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向,并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

    HIGH MOBILITY CMOS CIRCUITS
    65.
    发明申请
    HIGH MOBILITY CMOS CIRCUITS 有权
    高移动性CMOS电路

    公开(公告)号:US20080237720A1

    公开(公告)日:2008-10-02

    申请号:US11863757

    申请日:2007-09-28

    IPC分类号: H01L27/092

    摘要: Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

    摘要翻译: 在衬底上形成的半导体结构和形成半导体的工艺。 半导体包括具有场效应晶体管(FETS)的第一部分和场效应晶体管的第二部分的多个场效应晶体管。 第一应力层具有第一厚度并且被配置为向多个场效应晶体管的第一部分施加第一确定的应力。 第二应力层具有第二厚度,并且被配置为将第二确定的应力赋予多个场效应晶体管的第二部分。

    Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels
    66.
    发明授权
    Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels 有权
    应变硅直接绝缘体上的衬底,具有杂化晶体取向和不同的应力水平

    公开(公告)号:US07423303B2

    公开(公告)日:2008-09-09

    申请号:US11830464

    申请日:2007-07-30

    IPC分类号: H01L29/786

    摘要: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

    摘要翻译: 本发明提供了具有多个结晶取向的应变Si直接绝缘体(SSDOI)基板及其形成方法。 广义上,但是具体来说,本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层,所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向,并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

    Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels
    67.
    发明授权
    Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels 失效
    用于制造具有混合晶体取向和不同应力水平的应变硅绝缘体上基板的方法

    公开(公告)号:US07271043B2

    公开(公告)日:2007-09-18

    申请号:US11037622

    申请日:2005-01-18

    IPC分类号: H01L21/8238

    摘要: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

    摘要翻译: 本发明提供了具有多个结晶取向的应变Si直接绝缘体(SSDOI)基板及其形成方法。 广义上,但是具体来说,本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层,所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向,并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

    Dual function FinFET, finmemory and method of manufacture
    68.
    发明授权
    Dual function FinFET, finmemory and method of manufacture 有权
    双功能FinFET,Finmemory和制造方法

    公开(公告)号:US07087952B2

    公开(公告)日:2006-08-08

    申请号:US10978951

    申请日:2004-11-01

    IPC分类号: H01L29/788

    摘要: A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

    摘要翻译: Fin场效应晶体管(FinFET)中的非易失性存储单元以及形成包括非易失性存储单元的集成电路(IC)芯片的方法。 每个FET包括沿着半导体(例如硅)翅片的一侧的控制栅极,沿着鳍片的相对的浮动栅极和沿着浮动栅极的编程栅极。 通过调节浮动栅极上的电荷来调节控制栅极器件的阈值。

    High mobility CMOS circuits
    70.
    发明授权
    High mobility CMOS circuits 有权
    高移动性CMOS电路

    公开(公告)号:US08013392B2

    公开(公告)日:2011-09-06

    申请号:US11863757

    申请日:2007-09-28

    IPC分类号: H01L27/01

    摘要: Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

    摘要翻译: 在衬底上形成的半导体结构和形成半导体的工艺。 半导体包括具有场效应晶体管(FETS)的第一部分和场效应晶体管的第二部分的多个场效应晶体管。 第一应力层具有第一厚度并且被配置为向多个场效应晶体管的第一部分施加第一确定的应力。 第二应力层具有第二厚度,并且被配置为将第二确定的应力赋予多个场效应晶体管的第二部分。