公开(公告)号：US06335634B1

公开(公告)日：2002-01-01

申请号：US09577297

申请日：2000-05-22

申请人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

发明人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

IPC分类号： G06F738

CPC分类号： H03K19/17736 ,  H03K19/17792

摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

摘要翻译： 提供了用于在可编程逻辑器件上选择性地互连逻辑的可编程互连组布置。 互连组可以被编程为在设备上的各种导体之间路由信号，并且将信号从设备上的各种逻辑区域路由到各种导体。 互连组提供路由灵活性和效率，而不需要使用过多的互连资源。

公开(公告)号：US06323677B1

公开(公告)日：2001-11-27

申请号：US09542211

申请日：2000-04-04

申请人： Christopher F. Lane ,  Srinivas T. Reddy ,  Richard G. Cliff ,  Ketan H. Zaveri ,  Bruce B. Pedersen ,  Kerry Veenstra

发明人： Christopher F. Lane ,  Srinivas T. Reddy ,  Richard G. Cliff ,  Ketan H. Zaveri ,  Bruce B. Pedersen ,  Kerry Veenstra

IPC分类号： H03K19173

CPC分类号： H03K19/17792 ,  H03K19/17728 ,  H03K19/17732

摘要： In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

摘要翻译： 为了便于可编程逻辑器件中的乘法性能，这些器件的各个逻辑模块被构造成使得一个逻辑模块可以执行（至少）二进制乘法的一个位置和完全二进制加法的一个位置。 这使得可以减少执行乘法所需的逻辑模块的数量。 它还减少了乘法中使用的模块间连接的数量，从而倾向于减少执行乘法所需的时间。

公开(公告)号：US6066960A

公开(公告)日：2000-05-23

申请号：US82878

申请日：1998-05-21

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17728

摘要： AND gates are used at the inputs to logic elements in a programmable logic device. This allows more efficient configuration of the logic elements for basic functions such as a multiplier, clearable counter and multiplexer. Inputs to the AND gates are enabled by LAB-wide control signals that are distributed to several logic elements within a logic array block. The control signals can also be generated from a RAM or ROM, or by decoding existing control signals.

摘要翻译： 在可编程逻辑器件中的逻辑元件的输入端使用与门。 这允许更有效地配置用于基本功能的逻辑元件，例如乘法器，可清除计数器和多路复用器。 与门的输入由分布在逻辑阵列块内的多个逻辑元件的LAB范围的控制信号使能。 控制信号也可以从RAM或ROM生成，或通过解码现有的控制信号。

公开(公告)号：US06043676A

公开(公告)日：2000-03-28

申请号：US825821

申请日：1997-03-28

申请人： David W. Mendel ,  Brent A. Fairbanks ,  Bruce B. Pedersen

发明人： David W. Mendel ,  Brent A. Fairbanks ,  Bruce B. Pedersen

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： A programmable logic device (10) has a number of programmable logic elements (LES) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LAB incorporates one or more wide-input AND gates (74) for selectively combining the outputs of any number of LEs and producing a signal that is a logical combination of any number of its LEs. In variations of the invention, input signals may be selectively coupled to an AND gate by means of an OR gate (78) and may be selectively inverted by means of an XOR gate (76). A digital information processing system (500) incorporating the invention is disclosed. Various circuit techniques are provided for efficient implementation of a fast and wide exclusive OR or exclusive NOR function. A logic array block is equipped with a dedicated exclusive OR circuit with programmable inputs connected to selected terms from various logic cells, or outputs of the various logic cells. Another embodiment allows creating an embedded chain of exclusive OR gates to implement a wide exclusive OR gate by cascading a smaller exclusive OR gate within several logic cells.

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LES）（12），它们被分组在多个逻辑阵列块（LAB）中。 LAB包括一个或多个宽输入与门（74），用于选择性地组合任何数量的LE的输出，并产生作为任何数量的LE的逻辑组合的信号。 在本发明的变型中，输入信号可以通过或门（78）选择性地耦合到与门，并且可以通过异或门（76）选择性地反相。 公开了结合本发明的数字信息处理系统（500）。 提供了各种电路技术，用于有效地实现快速和宽泛的异或或异或NOR功能。 逻辑阵列块配备有专用异或电路，其可编程输入连接到来自各种逻辑单元的选定项或各种逻辑单元的输出。 另一实施例允许创建异或门的嵌入链以通过级联多个逻辑单元内的较小的异或门来实现宽的异或门。

公开(公告)号：US5963049A

公开(公告)日：1999-10-05

申请号：US807561

申请日：1997-02-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

公开(公告)号：US5936425A

公开(公告)日：1999-08-10

申请号：US96250

申请日：1998-06-11

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/1737 ,  H03K19/1778

摘要： Each output signal of programmable logic circuitry is made programmably available to drive one or more of a plurality of tri-statable input/output pins of the circuitry. Each output signal is also made programmably available to provide the output enable signal for one or more of a multiplicity of those input/output pins. The above-mentioned plurality and multiplicity associated with each output signal may include the same or different input/output pins. Output signals may therefore be routed to the input/output pins with greater flexibility, and output enable signal options are also greatly increased.

摘要翻译： 可编程逻辑电路的每个输出信号被编程地可用于驱动电路的多个三态输入/输出引脚中的一个或多个。 每个输出信号也可编程地可用于为多个输入/输出引脚中的一个或多个提供输出使能信号。 与每个输出信号相关联的上述多个和多重可以包括相同或不同的输入/输出引脚。 因此，输出信号可以以更大的灵活性被路由到输入/输出引脚，并且输出使能信号选项也大大增加。

公开(公告)号：US5898318A

公开(公告)日：1999-04-27

申请号：US497100

申请日：1995-06-30

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被分组在多个逻辑阵列块（LAB）中。 提供了一种全局互连结构（20,24），用于将LAB与其他LAB相互连接。 相邻或附近的LE可通过LE之间的级联连接器（72）彼此连接。 通过提供允许来自一个LE的级联线通过级联逻辑门（94）选择性地耦合到相邻或附近LE的输入的选择器（90）来增强级联。

公开(公告)号：US5859542A

公开(公告)日：1999-01-12

申请号：US898541

申请日：1997-07-22

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABS) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被组合在多个逻辑阵列块（LABS）（14）中。 提供了一种全局互连结构（20,24），用于将LAB与其他LAB相互连接。 相邻或附近的LE可通过LE之间的级联连接器（72）彼此连接。 通过提供允许来自一个LE的级联线通过级联逻辑门（94）选择性地耦合到相邻或附近LE的输入的选择器（90）来增强级联。

公开(公告)号：US5815003A

公开(公告)日：1998-09-29

申请号：US497632

申请日：1995-06-30

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LE incorporates a plurality of partitioned look-up tables (40a, 40b) that may be selectively connected to its inputs and outputs by means of a number of multiplexers (44a-d, 46). Shared LAB-wide input lines (43a, 43b) provide a shared input line into a number of LEs in a LAB. A digital information processing system (500) incorporating the invention is disclosed. A wide-input AND gate (74) combining the outputs of a number of LEs is disclosed.

摘要翻译： 可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被分组在多个逻辑阵列块（LAB）中。 LE包括多个分割的查找表（40a，40b），其可以通过多个多路复用器（44a-d，46）选择性地连接到其输入和输出。 共享LAB宽输入线（43a，43b）为LAB中的许多LE提供共享输入线。 公开了结合本发明的数字信息处理系统（500）。 公开了组合多个LE的输出的宽输入与门（74）。

公开(公告)号：US5787009A

公开(公告)日：1998-07-28

申请号：US603222

申请日：1996-02-20

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Partitioning of a circuit design to facilitate economical implementation of that circuit in a physical circuit that is made up of two or more physical subcircuits is improved by starting with two different, conventionally produced partitions of the design and combining selected features of those two starting partitions to produce a final partition that is better than either of the starting partitions.